> entity is a VHDL word, as well as if. > foo is a made up word. >
It's also for the VHDL reserved words process, case, architecture. I can't believe VIM can't fold reserved words? Or is this a bug? I did change entity into entit (so removing the y char) in the given syn region. When I now type entit in my VHDL file the word is not higlighted as a VHDL word and the folding goes ok. Why doesn't it work for real VHDL words? Rgds, Jeri -- You received this message from the "vim_use" maillist. Do not top-post! Type your reply below the text you are replying to. For more information, visit http://www.vim.org/maillist.php
