Hello All, I have run into a problem when using Vim in Verilog and am hoping you can help. The problem has to do with the ternary operator.
I have a file that looks like this: wire [31:0] modified_value_w; ... assign modified_value_w = (some_register_r & read_wire_w); assign result_w = enable_w?modified_value_w:some_other_wire_w; When I search for \<modified_value_w\>, Vim only finds this first 2 lines. this is because the 3rd line doesn't have whitespace around the "?" Vim treats the "?" Character as a keyword for Verilog, because it can be part of a number (ex: 16'b? ) My question is: Is there a way to get Vim to treat "?" as a keyword when used in a number, but not when it's being used as a ternary operator? Thanks in Advance, Sean -- -- You received this message from the "vim_use" maillist. Do not top-post! Type your reply below the text you are replying to. For more information, visit http://www.vim.org/maillist.php --- You received this message because you are subscribed to the Google Groups "vim_use" group. To unsubscribe from this group and stop receiving emails from it, send an email to vim_use+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout.