https://bugs.freebsd.org/bugzilla/show_bug.cgi?id=277559
--- Comment #6 from John F. Carr <[email protected]> --- I noticed that the instruction cache types are different for the two processor types. A-53 is virtually indexed and A-72 is physically indexed. Cache Type = <64 byte D-cacheline,64 byte I-cacheline,VIPT ICache,64 byte ERG,64 byte CWG> Cache Type = <64 byte D-cacheline,64 byte I-cacheline,PIPT ICache,64 byte ERG,64 byte CWG> When changing address translation for EL2 code, are any cache clean operations required? handle_hyp_init currently contains a TLB flush and isb. -- You are receiving this mail because: You are the assignee for the bug.
