On 03/06/2013 01:21 AM, Michael S. Tsirkin wrote:
>
> Right. Though even with better granularify bridge windows
> would still be a (smaller) problem causing fragmentation.
>
> If we were to extend the PCI spec I would go for a bridge without
> windows at all: a bridge can snoop on configuration transactions and
> responses programming devices behind it and build a full map of address
> to device mappings.
>
> In partucular, this would be a good fit for an uplink bridge in a PCI
> express switch, which is integrated with downlink bridges on the same
> silicon, so bridge windows do nothing but add overhead.
>
True, but the real problem is that the downlink (type 1 header) is
typically on a different piece of silicon than the device BAR (type 0
header).
I am not sure that a snooping-based system will work and not be
prohibitive in its hardware cost on an actual hardware system. I
suspect it would decay into needing a large RAM array in every bridge.
-hpa
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