On Thursday 2 March 2006 10:37, Tomas Vilda wrote: > > then traffic program will do socket, setsockopt, bind and then go to > function sink and will wait for packets. But I do not get any packets in > this case.
Then you should check that the card actually receives traffic on the D channel by putting the driver in debug mode. > Sorry, I missused the word perfomance, I have in mind that if I will have 16 > hfc-e1 chips in one computer with larger FIFO we could make less requests > from driver with bigger read buffer size. No, the driver will still receive one IRQ for every frame, there is no performances gain by having deeper FIFOs, you just lowere the chance to have fifo underflows/overflows under heavy system load. > Less request with bigger buffer on one read = faster. It's not how the HFC FIFOs work. > Because I worry that server cann't cope with all streams > and we can lose some data with using only onboard RAM. This is another matter, however, with systems available nowadays, handling 2 Mbit/s is not a problem and the current interrupt latencies are much smaller than the minimum FIFO size multiplited by octet time. Anyway, before or later the RAM configuration parameter will begin working so, I wouldn't worry at all. > Maybe you have experience and can say something about that? In our case with > maximum usage of B channels that is 30 Bchannels * 16hfc-e1 chips = 480 B > channels reading and writing to disc (additionally decoding layer 3 on all D > channels) on one server. You will probably hit the FIFO selection bottleneck before saturating the CPU bandwidth. Bye, -- Daniele Orlandi _______________________________________________ Visdn-hackers mailing list [email protected] https://mailman.uli.it/mailman/listinfo/visdn-hackers
