From: Damjan Marion <dmar...@me.com> Sent: Friday, March 22, 2019 3:59 PM To: Nitin Saxena <nsax...@marvell.com> Cc: vpp-dev@lists.fd.io; Narayana Prasad Raju Athreya <pathr...@marvell.com> Subject: Re: [EXT] [vpp-dev] 128 byte cache line support
On 22 Mar 2019, at 09:35, Nitin Saxena <nsax...@marvell.com<mailto:nsax...@marvell.com>> wrote: Hi Damjan, >> Can we conclude that there is no technical arguments? On technical aspects: 1. Changing VLIB structure to 128 byte from current 256 byte (for our target) * In case of forwarding we only use single Dcache line till ipv4-input (because of packet parsing info in second 64B of vlib). The second cache line, which is data, being accessed only in ipv4-lookup and ipv4-rewrite node. With the proposal we have to put our hardware parsing information to HEADROOM, thereby increasing one cache line access to every node. This will impact performance for us. I don't think this is technical argument, it falls to me under tecnical depth category. Just for my curiosity, what’s wrong with putting your data into vlib_buffer_t-> opaque2 ? [Nitin]: So 56 byte of opaque2 data should be fine if nobody overwrites to it in stack. In that case we prefer to have opaque2 data at 64 byte aligned position (just after cacheline1 marker). Then I am fine with the proposal. * 1. Changing remaining per-thread structures to 128B * This proposal looks fine for other data structures. However: i. You already mentioned that in worst case there will be two prefetches of 64B but in our processor second prefetch should be ignored. I checked internally and yes the second prefetch will be ignored if the two prefetches are very close. However the second prefetch will not be ignored on the very first instruction pipeline. So I feel its wastage of few pipelining stages per packet. Otherwise it looks fine to me. So here we just have your feeling, no real arguments, so i guess it is fine...
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