<snip>
>
> >>> Issue #1: VPP crashes when scales to multiple worker cores/threads.
> [...]
> >>> We guess VPP buffer metadata has been corrupted in the case of
> >>> multiple worker threads using VPP release version
>
> >> BG: do you reproduce the issue on both x86 and ARM? Or only on ARM?
> >> I’m especially thinking about difference in memory coherency that
> >> could bite us here…
>
> > [Honnappa] On Arm, the barriers for working with MMIO are different
> > than the ones used for normal shared memory. Currently, in VPP, this
> > distinction does not exist (please correct me if I am wrong).
>
> Yes, I was thinking about something along that line. Currently we use
> CLIB_MEMORY_STORE_BARRIER() defined as __builtin_ia32_sfence() on x86
> and __sync_synchronize() on ARM.
> __sync_synchronize() should be a full memory barrier but is it enough for
> MMIO on ARM?
Yes, this is the code I am referring to. That is not enough. It generates 'dmb
ish'.
We need to use 'dmb oshst' for store-store barrier and 'dmb oshld' for
load-load barrier.
I would suggest defining 3 new APIs:
xxx_io_mb() - Full barrier (on ARM, 'dmb osh')
xxx_io_rmb() - load-load barrier ('dmb oshld')
xxx_io_wmb() - store-store barrier ('dmd oshst')
I do not think there are any compiler intrinsics that generate these
instructions.
>
> Best
> ben
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