Diff
Modified: trunk/Source/_javascript_Core/ChangeLog (234873 => 234874)
--- trunk/Source/_javascript_Core/ChangeLog 2018-08-15 00:30:50 UTC (rev 234873)
+++ trunk/Source/_javascript_Core/ChangeLog 2018-08-15 00:50:50 UTC (rev 234874)
@@ -1,3 +1,35 @@
+2018-08-14 Yusuke Suzuki <[email protected]>
+
+ [JSC] Add GPRReg::InvalidGPRReg and FPRReg::InvalidFPRReg
+ https://bugs.webkit.org/show_bug.cgi?id=188589
+
+ Reviewed by Mark Lam.
+
+ Since GPRReg(RegisterID) and FPRReg(FPRegisterID) do not include -1 in their enum values,
+ UBSan dumps bunch of warnings "runtime error: load of value 4294967295, which is not a valid value for type 'RegisterID'".
+
+ 1. We add InvalidGPRReg and InvalidFPRReg to enum values of GPRReg and FPRReg to suppress the above warnings.
+ 2. We make GPRReg and FPRReg int8_t enums.
+ 3. We replace `#define InvalidGPRReg ((JSC::GPRReg)-1)` to `static constexpr GPRReg InvalidGPRReg { GPRReg::InvalidGPRReg };`.
+
+ * assembler/ARM64Assembler.h:
+ * assembler/ARMAssembler.h:
+ * assembler/ARMv7Assembler.h:
+ * assembler/MIPSAssembler.h:
+ * assembler/X86Assembler.h:
+ * jit/FPRInfo.h:
+ * jit/GPRInfo.h:
+ (JSC::JSValueRegs::JSValueRegs):
+ (JSC::JSValueRegs::tagGPR const):
+ (JSC::JSValueRegs::payloadGPR const):
+ (JSC::JSValueSource::JSValueSource):
+ (JSC::JSValueSource::unboxedCell):
+ (JSC::JSValueSource::operator bool const):
+ (JSC::JSValueSource::base const):
+ (JSC::JSValueSource::tagGPR const):
+ (JSC::JSValueSource::payloadGPR const):
+ (JSC::JSValueSource::hasKnownTag const):
+
2018-08-14 Keith Miller <[email protected]>
Add missing availability macro.
Modified: trunk/Source/_javascript_Core/assembler/ARM64Assembler.h (234873 => 234874)
--- trunk/Source/_javascript_Core/assembler/ARM64Assembler.h 2018-08-15 00:30:50 UTC (rev 234873)
+++ trunk/Source/_javascript_Core/assembler/ARM64Assembler.h 2018-08-15 00:50:50 UTC (rev 234874)
@@ -162,7 +162,7 @@
namespace ARM64Registers {
-typedef enum {
+typedef enum : int8_t {
// Parameter/result registers.
x0,
x1,
@@ -208,9 +208,10 @@
x29 = fp,
x30 = lr,
zr = 0x3f,
+ InvalidGPRReg = -1,
} RegisterID;
-typedef enum {
+typedef enum : int8_t {
pc,
nzcv,
fpsr
@@ -219,7 +220,7 @@
// ARM64 always has 32 FPU registers 128-bits each. See http://llvm.org/devmtg/2012-11/Northover-AArch64.pdf
// and Section 5.1.2 in http://infocenter.arm.com/help/topic/com.arm.doc.ihi0055b/IHI0055B_aapcs64.pdf.
// However, we only use them for 64-bit doubles.
-typedef enum {
+typedef enum : int8_t {
// Parameter/result registers.
q0,
q1,
@@ -255,6 +256,7 @@
q29,
q30,
q31,
+ InvalidFPRReg = -1,
} FPRegisterID;
static constexpr bool isSp(RegisterID reg) { return reg == sp; }
Modified: trunk/Source/_javascript_Core/assembler/ARMAssembler.h (234873 => 234874)
--- trunk/Source/_javascript_Core/assembler/ARMAssembler.h 2018-08-15 00:30:50 UTC (rev 234873)
+++ trunk/Source/_javascript_Core/assembler/ARMAssembler.h 2018-08-15 00:50:50 UTC (rev 234874)
@@ -38,7 +38,7 @@
namespace ARMRegisters {
- typedef enum {
+ typedef enum : int8_t {
r0,
r1,
r2,
@@ -62,15 +62,16 @@
r12 = ip, S1 = ip,
r13 = sp,
r14 = lr,
- r15 = pc
+ r15 = pc,
+ InvalidGPRReg = -1,
} RegisterID;
- typedef enum {
+ typedef enum : int8_t {
apsr,
fpscr
} SPRegisterID;
- typedef enum {
+ typedef enum : int8_t {
d0,
d1,
d2,
@@ -105,6 +106,7 @@
d30,
d31,
#endif // CPU(ARM_NEON) || CPU(ARM_VFP_V3_D32)
+ InvalidFPRReg = -1,
} FPRegisterID;
} // namespace ARMRegisters
Modified: trunk/Source/_javascript_Core/assembler/ARMv7Assembler.h (234873 => 234874)
--- trunk/Source/_javascript_Core/assembler/ARMv7Assembler.h 2018-08-15 00:30:50 UTC (rev 234873)
+++ trunk/Source/_javascript_Core/assembler/ARMv7Assembler.h 2018-08-15 00:50:50 UTC (rev 234874)
@@ -39,7 +39,7 @@
namespace ARMRegisters {
- typedef enum {
+ typedef enum : int8_t {
r0,
r1,
r2,
@@ -63,15 +63,16 @@
ip = r12,
sp = r13,
lr = r14,
- pc = r15
+ pc = r15,
+ InvalidGPRReg = -1,
} RegisterID;
- typedef enum {
+ typedef enum : int8_t {
apsr,
fpscr
} SPRegisterID;
- typedef enum {
+ typedef enum : int8_t {
s0,
s1,
s2,
@@ -106,7 +107,7 @@
s31,
} FPSingleRegisterID;
- typedef enum {
+ typedef enum : int8_t {
d0,
d1,
d2,
@@ -141,10 +142,11 @@
d30,
d31,
#endif // CPU(ARM_NEON) || CPU(ARM_VFP_V3_D32)
+ InvalidFPRReg = -1,
} FPDoubleRegisterID;
#if CPU(ARM_NEON)
- typedef enum {
+ typedef enum : int8_t {
q0,
q1,
q2,
Modified: trunk/Source/_javascript_Core/assembler/MIPSAssembler.h (234873 => 234874)
--- trunk/Source/_javascript_Core/assembler/MIPSAssembler.h 2018-08-15 00:30:50 UTC (rev 234873)
+++ trunk/Source/_javascript_Core/assembler/MIPSAssembler.h 2018-08-15 00:50:50 UTC (rev 234874)
@@ -41,7 +41,7 @@
typedef uint32_t MIPSWord;
namespace MIPSRegisters {
-typedef enum {
+typedef enum : int8_t {
r0 = 0,
r1,
r2,
@@ -105,10 +105,11 @@
gp = r28,
sp = r29,
fp = r30,
- ra = r31
+ ra = r31,
+ InvalidGPRReg = -1,
} RegisterID;
-typedef enum {
+typedef enum : int8_t {
fir = 0,
fccr = 25,
fexr = 26,
@@ -117,7 +118,7 @@
pc
} SPRegisterID;
-typedef enum {
+typedef enum : int8_t {
f0,
f1,
f2,
@@ -149,7 +150,8 @@
f28,
f29,
f30,
- f31
+ f31,
+ InvalidFPRReg = -1,
} FPRegisterID;
} // namespace MIPSRegisters
Modified: trunk/Source/_javascript_Core/assembler/X86Assembler.h (234873 => 234874)
--- trunk/Source/_javascript_Core/assembler/X86Assembler.h 2018-08-15 00:30:50 UTC (rev 234873)
+++ trunk/Source/_javascript_Core/assembler/X86Assembler.h 2018-08-15 00:50:50 UTC (rev 234874)
@@ -41,7 +41,7 @@
namespace X86Registers {
-typedef enum {
+typedef enum : int8_t {
eax,
ecx,
edx,
@@ -58,16 +58,17 @@
r12,
r13,
r14,
- r15
+ r15,
#endif
+ InvalidGPRReg = -1,
} RegisterID;
-typedef enum {
+typedef enum : int8_t {
eip,
eflags
} SPRegisterID;
-typedef enum {
+typedef enum : int8_t {
xmm0,
xmm1,
xmm2,
@@ -84,8 +85,9 @@
xmm12,
xmm13,
xmm14,
- xmm15
+ xmm15,
#endif
+ InvalidFPRReg = -1,
} XMMRegisterID;
} // namespace X86Register
Modified: trunk/Source/_javascript_Core/jit/CCallHelpers.h (234873 => 234874)
--- trunk/Source/_javascript_Core/jit/CCallHelpers.h 2018-08-15 00:30:50 UTC (rev 234873)
+++ trunk/Source/_javascript_Core/jit/CCallHelpers.h 2018-08-15 00:50:50 UTC (rev 234874)
@@ -314,7 +314,7 @@
std::array<RegType, TargetSize> result { };
for (unsigned i = 0; i < TargetSize; i++) {
- ASSERT(sourceArray[i] != InfoTypeForReg<RegType>::InvalidIndex);
+ ASSERT(sourceArray[i] != static_cast<int32_t>(InfoTypeForReg<RegType>::InvalidIndex));
result[i] = sourceArray[i];
}
Modified: trunk/Source/_javascript_Core/jit/FPRInfo.h (234873 => 234874)
--- trunk/Source/_javascript_Core/jit/FPRInfo.h 2018-08-15 00:30:50 UTC (rev 234873)
+++ trunk/Source/_javascript_Core/jit/FPRInfo.h 2018-08-15 00:50:50 UTC (rev 234874)
@@ -31,7 +31,7 @@
namespace JSC {
typedef MacroAssembler::FPRegisterID FPRReg;
-#define InvalidFPRReg ((::JSC::FPRReg)-1)
+static constexpr FPRReg InvalidFPRReg { FPRReg::InvalidFPRReg };
#if ENABLE(JIT)
Modified: trunk/Source/_javascript_Core/jit/GPRInfo.h (234873 => 234874)
--- trunk/Source/_javascript_Core/jit/GPRInfo.h 2018-08-15 00:30:50 UTC (rev 234873)
+++ trunk/Source/_javascript_Core/jit/GPRInfo.h 2018-08-15 00:50:50 UTC (rev 234874)
@@ -39,7 +39,7 @@
// top of the LowLevelInterpreter.asm file.
typedef MacroAssembler::RegisterID GPRReg;
-#define InvalidGPRReg ((::JSC::GPRReg)-1)
+static constexpr GPRReg InvalidGPRReg { GPRReg::InvalidGPRReg };
#if ENABLE(JIT)
@@ -161,8 +161,8 @@
class JSValueRegs {
public:
JSValueRegs()
- : m_tagGPR(static_cast<int8_t>(InvalidGPRReg))
- , m_payloadGPR(static_cast<int8_t>(InvalidGPRReg))
+ : m_tagGPR(InvalidGPRReg)
+ , m_payloadGPR(InvalidGPRReg)
{
}
@@ -196,8 +196,8 @@
}
bool operator!=(JSValueRegs other) const { return !(*this == other); }
- GPRReg tagGPR() const { return static_cast<GPRReg>(m_tagGPR); }
- GPRReg payloadGPR() const { return static_cast<GPRReg>(m_payloadGPR); }
+ GPRReg tagGPR() const { return m_tagGPR; }
+ GPRReg payloadGPR() const { return m_payloadGPR; }
GPRReg gpr(WhichValueWord which) const
{
switch (which) {
@@ -215,8 +215,8 @@
void dump(PrintStream&) const;
private:
- int8_t m_tagGPR;
- int8_t m_payloadGPR;
+ GPRReg m_tagGPR;
+ GPRReg m_payloadGPR;
};
class JSValueSource {
@@ -223,8 +223,8 @@
public:
JSValueSource()
: m_offset(notAddress())
- , m_baseOrTag(static_cast<int8_t>(InvalidGPRReg))
- , m_payload(static_cast<int8_t>(InvalidGPRReg))
+ , m_baseOrTag(InvalidGPRReg)
+ , m_payload(InvalidGPRReg)
, m_tagType(0)
{
}
@@ -239,8 +239,8 @@
JSValueSource(GPRReg tagGPR, GPRReg payloadGPR)
: m_offset(notAddress())
- , m_baseOrTag(static_cast<int8_t>(tagGPR))
- , m_payload(static_cast<int8_t>(payloadGPR))
+ , m_baseOrTag(tagGPR)
+ , m_payload(payloadGPR)
, m_tagType(0)
{
}
@@ -247,12 +247,12 @@
JSValueSource(MacroAssembler::Address address)
: m_offset(address.offset)
- , m_baseOrTag(static_cast<int8_t>(address.base))
- , m_payload(static_cast<int8_t>(InvalidGPRReg))
+ , m_baseOrTag(address.base)
+ , m_payload(InvalidGPRReg)
, m_tagType(0)
{
ASSERT(m_offset != notAddress());
- ASSERT(static_cast<GPRReg>(m_baseOrTag) != InvalidGPRReg);
+ ASSERT(m_baseOrTag != InvalidGPRReg);
}
static JSValueSource unboxedCell(GPRReg payloadGPR)
@@ -259,8 +259,8 @@
{
JSValueSource result;
result.m_offset = notAddress();
- result.m_baseOrTag = static_cast<int8_t>(InvalidGPRReg);
- result.m_payload = static_cast<int8_t>(payloadGPR);
+ result.m_baseOrTag = InvalidGPRReg;
+ result.m_payload = payloadGPR;
result.m_tagType = static_cast<int8_t>(JSValue::CellTag);
return result;
}
@@ -268,8 +268,7 @@
bool operator!() const { return !static_cast<bool>(*this); }
explicit operator bool() const
{
- return static_cast<GPRReg>(m_baseOrTag) != InvalidGPRReg
- || static_cast<GPRReg>(m_payload) != InvalidGPRReg;
+ return m_baseOrTag != InvalidGPRReg || m_payload != InvalidGPRReg;
}
bool isAddress() const
@@ -287,19 +286,19 @@
GPRReg base() const
{
ASSERT(isAddress());
- return static_cast<GPRReg>(m_baseOrTag);
+ return m_baseOrTag;
}
GPRReg tagGPR() const
{
- ASSERT(!isAddress() && static_cast<GPRReg>(m_baseOrTag) != InvalidGPRReg);
- return static_cast<GPRReg>(m_baseOrTag);
+ ASSERT(!isAddress() && m_baseOrTag != InvalidGPRReg);
+ return m_baseOrTag;
}
GPRReg payloadGPR() const
{
ASSERT(!isAddress());
- return static_cast<GPRReg>(m_payload);
+ return m_payload;
}
bool hasKnownTag() const
@@ -306,7 +305,7 @@
{
ASSERT(!!*this);
ASSERT(!isAddress());
- return static_cast<GPRReg>(m_baseOrTag) == InvalidGPRReg;
+ return m_baseOrTag == InvalidGPRReg;
}
uint32_t tag() const
@@ -325,8 +324,8 @@
static inline int32_t notAddress() { return 0x80000000; }
int32_t m_offset;
- int8_t m_baseOrTag;
- int8_t m_payload;
+ GPRReg m_baseOrTag;
+ GPRReg m_payload;
int8_t m_tagType; // Contains the low bits of the tag.
};
#endif // USE(JSVALUE32_64)
Modified: trunk/Source/WebCore/ChangeLog (234873 => 234874)
--- trunk/Source/WebCore/ChangeLog 2018-08-15 00:30:50 UTC (rev 234873)
+++ trunk/Source/WebCore/ChangeLog 2018-08-15 00:50:50 UTC (rev 234874)
@@ -1,3 +1,17 @@
+2018-08-14 Yusuke Suzuki <[email protected]>
+
+ [JSC] Add GPRReg::InvalidGPRReg and FPRReg::InvalidFPRReg
+ https://bugs.webkit.org/show_bug.cgi?id=188589
+
+ Reviewed by Mark Lam.
+
+ No behavior change.
+
+ * cssjit/FunctionCall.h:
+ (WebCore::FunctionCall::FunctionCall):
+ * cssjit/SelectorCompiler.cpp:
+ (WebCore::SelectorCompiler::SelectorCodeGenerator::modulo):
+
2018-08-14 Alex Christensen <[email protected]>
isValidCSSSelector is unsafe to be called from a non-main thread
Modified: trunk/Source/WebCore/cssjit/FunctionCall.h (234873 => 234874)
--- trunk/Source/WebCore/cssjit/FunctionCall.h 2018-08-15 00:30:50 UTC (rev 234873)
+++ trunk/Source/WebCore/cssjit/FunctionCall.h 2018-08-15 00:50:50 UTC (rev 234874)
@@ -43,8 +43,8 @@
, m_stackAllocator(stackAllocator)
, m_callRegistry(callRegistry)
, m_argumentCount(0)
- , m_firstArgument(InvalidGPRReg)
- , m_secondArgument(InvalidGPRReg)
+ , m_firstArgument(JSC::InvalidGPRReg)
+ , m_secondArgument(JSC::InvalidGPRReg)
{
}
Modified: trunk/Source/WebCore/cssjit/SelectorCompiler.cpp (234873 => 234874)
--- trunk/Source/WebCore/cssjit/SelectorCompiler.cpp 2018-08-15 00:30:50 UTC (rev 234873)
+++ trunk/Source/WebCore/cssjit/SelectorCompiler.cpp 2018-08-15 00:50:50 UTC (rev 234874)
@@ -2378,7 +2378,7 @@
Assembler::RegisterID dividend = JSC::X86Registers::eax;
RegisterAllocationType dividendAllocation = RegisterAllocationType::External;
StackAllocator::StackReference temporaryDividendStackReference;
- Assembler::RegisterID temporaryDividendCopy = InvalidGPRReg;
+ Assembler::RegisterID temporaryDividendCopy = JSC::InvalidGPRReg;
if (inputDividend != dividend) {
bool registerIsInUse = m_registerAllocator.allocatedRegisters().contains(dividend);
if (registerIsInUse) {
@@ -2400,7 +2400,7 @@
Assembler::RegisterID remainder = JSC::X86Registers::edx;
RegisterAllocationType remainderAllocation = RegisterAllocationType::External;
StackAllocator::StackReference temporaryRemainderStackReference;
- Assembler::RegisterID temporaryRemainderCopy = InvalidGPRReg;
+ Assembler::RegisterID temporaryRemainderCopy = JSC::InvalidGPRReg;
if (inputDividend != remainder) {
bool registerIsInUse = m_registerAllocator.allocatedRegisters().contains(remainder);
if (registerIsInUse) {
