Diff
Modified: trunk/Source/_javascript_Core/ChangeLog (287511 => 287512)
--- trunk/Source/_javascript_Core/ChangeLog 2022-01-02 09:07:58 UTC (rev 287511)
+++ trunk/Source/_javascript_Core/ChangeLog 2022-01-02 09:12:42 UTC (rev 287512)
@@ -1,5 +1,32 @@
2022-01-02 Zan Dobersek <zdober...@igalia.com>
+ [RISCV64] Enable building LLInt WebAssembly via the riscv64 offlineasm backend
+ https://bugs.webkit.org/show_bug.cgi?id=234776
+
+ Reviewed by Yusuke Suzuki.
+
+ Sprinkle RISCV64 conditions around WebAssembly.asm as appropriate.
+ For division, we can reuse the divi(s)/divq(s) instructions already
+ available in offlineasm. RISC-V additionally provides remainder
+ instructions, so the necessary offlineasm instructions are added
+ and used for RISCV64.
+
+ In the offlineasm riscv64 backend, the division and remainder
+ instruction handling is improved to properly cover signed and unsigned
+ variants. For other instructions used in LLint WebAssembly
+ implementation like left or right rotation, trailing- or leading-zero
+ counting, order-based floating-point comparison, load-reserved and
+ store-conditional operations, the riscv64WASMPlaceholder helper is used
+ to generate an ebreak instruction that will halt the program at runtime
+ but will not throw a build-time error. Proper implementations will be
+ provided once WebAssembly support on RISCV64 is taken up.
+
+ * llint/WebAssembly.asm:
+ * offlineasm/instructions.rb:
+ * offlineasm/riscv64.rb:
+
+2022-01-02 Zan Dobersek <zdober...@igalia.com>
+
[RISCV64] Get testmasm building for CPU(RISCV64)
https://bugs.webkit.org/show_bug.cgi?id=234774
Modified: trunk/Source/_javascript_Core/llint/WebAssembly.asm (287511 => 287512)
--- trunk/Source/_javascript_Core/llint/WebAssembly.asm 2022-01-02 09:07:58 UTC (rev 287511)
+++ trunk/Source/_javascript_Core/llint/WebAssembly.asm 2022-01-02 09:12:42 UTC (rev 287512)
@@ -32,7 +32,7 @@
if X86_64
const NumberOfWasmArgumentGPRs = 6
-elsif ARM64 or ARM64E
+elsif ARM64 or ARM64E or RISCV64
const NumberOfWasmArgumentGPRs = 8
else
error
@@ -50,7 +50,7 @@
# This must match the definition in LowLevelInterpreter.asm
if X86_64
const PB = csr2
-elsif ARM64 or ARM64E
+elsif ARM64 or ARM64E or RISCV64
const PB = csr7
else
error
@@ -198,7 +198,7 @@
subp CalleeSaveSpaceStackAligned, sp
if ARM64 or ARM64E
emit "stp x19, x26, [x29, #-16]"
- elsif X86_64
+ elsif X86_64 or RISCV64
storep PB, -0x8[cfr]
storep wasmInstance, -0x10[cfr]
else
@@ -212,7 +212,7 @@
# to be observable within the same Wasm module.
if ARM64 or ARM64E
emit "ldp x19, x26, [x29, #-16]"
- elsif X86_64
+ elsif X86_64 or RISCV64
loadp -0x8[cfr], PB
loadp -0x10[cfr], wasmInstance
else
@@ -996,7 +996,7 @@
# https://bugs.webkit.org/show_bug.cgi?id=203692
cdqi
idivi t1
- elsif ARM64 or ARM64E
+ elsif ARM64 or ARM64E or RISCV64
divis t1, t0
else
error
@@ -1019,7 +1019,7 @@
if X86_64
xori t2, t2
udivi t1
- elsif ARM64 or ARM64E
+ elsif ARM64 or ARM64E or RISCV64
divi t1, t0
else
error
@@ -1052,6 +1052,8 @@
divis t1, t0, t2
muli t1, t2
subi t0, t2, t2
+ elsif RISCV64
+ remis t1, t0
else
error
end
@@ -1076,6 +1078,8 @@
divi t1, t0, t2
muli t1, t2
subi t0, t2, t2
+ elsif RISCV64
+ remi t1, t0
else
error
end
@@ -1115,7 +1119,7 @@
# https://bugs.webkit.org/show_bug.cgi?id=203692
cqoq
idivq t1
- elsif ARM64 or ARM64E
+ elsif ARM64 or ARM64E or RISCV64
divqs t1, t0
else
error
@@ -1138,7 +1142,7 @@
if X86_64
xorq t2, t2
udivq t1
- elsif ARM64 or ARM64E
+ elsif ARM64 or ARM64E or RISCV64
divq t1, t0
else
error
@@ -1171,6 +1175,8 @@
divqs t1, t0, t2
mulq t1, t2
subq t0, t2, t2
+ elsif RISCV64
+ remqs t1, t0
else
error
end
@@ -1195,6 +1201,8 @@
divq t1, t0, t2
mulq t1, t2
subq t0, t2, t2
+ elsif RISCV64
+ remq t1, t0
else
error
end
@@ -1596,7 +1604,7 @@
mloadq(ctx, m_operand, t0)
if X86_64
cq2f t0, t1, ft0
- elsif ARM64 or ARM64E
+ elsif ARM64 or ARM64E or RISCV64
cq2f t0, ft0
else
error
@@ -1608,7 +1616,7 @@
mloadq(ctx, m_operand, t0)
if X86_64
cq2d t0, t1, ft0
- elsif ARM64 or ARM64E
+ elsif ARM64 or ARM64E or RISCV64
cq2d t0, ft0
else
error
Modified: trunk/Source/_javascript_Core/offlineasm/instructions.rb (287511 => 287512)
--- trunk/Source/_javascript_Core/offlineasm/instructions.rb 2022-01-02 09:07:58 UTC (rev 287511)
+++ trunk/Source/_javascript_Core/offlineasm/instructions.rb 2022-01-02 09:12:42 UTC (rev 287512)
@@ -387,10 +387,6 @@
"bfiq", # Bit field insert <source reg> <last bit written> <width immediate> <dest reg>
"pcrtoaddr", # Address from PC relative offset - adr instruction
"globaladdr",
- "divi",
- "divis",
- "divq",
- "divqs",
"notq",
"loadlinkacqb",
"loadlinkacqh",
@@ -438,7 +434,15 @@
"addis", # Add integers and set a flag.
"subis", # Same, but for subtraction.
"oris", # Same, but for bitwise or.
- "addps" # addis but for pointers.
+ "addps", # addis but for pointers.
+ "divi",
+ "divis",
+ "divq",
+ "divqs",
+ "remi",
+ "remis",
+ "remq",
+ "remqs"
]
MIPS_INSTRUCTIONS =
Modified: trunk/Source/_javascript_Core/offlineasm/riscv64.rb (287511 => 287512)
--- trunk/Source/_javascript_Core/offlineasm/riscv64.rb 2022-01-02 09:07:58 UTC (rev 287511)
+++ trunk/Source/_javascript_Core/offlineasm/riscv64.rb 2022-01-02 09:12:42 UTC (rev 287512)
@@ -113,6 +113,10 @@
raise "Not supported for RISCV64"
end
+def riscv64WASMPlaceholder
+ $asm.puts "ebreak"
+end
+
def riscv64LoadInstruction(size)
case size
when :b
@@ -335,8 +339,14 @@
case operation
when :mul
size == :w ? "mulw" : "mul"
+ when :divu
+ size == :w ? "divuw" : "divu"
when :div
- size == :w ? "divuw" : "divu"
+ size == :w ? "divw" : "div"
+ when :remu
+ size == :w ? "remuw" : "remu"
+ when :rem
+ size == :w ? "remw" : "rem"
else
raise "Unsupported arithmetic operation"
end
@@ -1545,11 +1555,21 @@
when "mulp", "mulq"
riscv64EmitMulDivArithmetic(operands, :d, :mul)
when "divi"
+ riscv64EmitMulDivArithmetic(operands, :w, :divu)
+ when "divq"
+ riscv64EmitMulDivArithmetic(operands, :d, :divu)
+ when "divis"
riscv64EmitMulDivArithmetic(operands, :w, :div)
- when "divq"
+ when "divqs"
riscv64EmitMulDivArithmetic(operands, :d, :div)
- when "divis", "divqs"
- riscv64RaiseUnsupported
+ when "remi"
+ riscv64EmitMulDivArithmetic(operands, :w, :remu)
+ when "remq"
+ riscv64EmitMulDivArithmetic(operands, :d, :rem)
+ when "remis"
+ riscv64EmitMulDivArithmetic(operands, :w, :rem)
+ when "remqs"
+ riscv64EmitMulDivArithmetic(operands, :d, :rem)
when "negi"
riscv64EmitComplementOperation(operands, :w, :neg)
when "negp", "negq"
@@ -1939,9 +1959,9 @@
riscv64RaiseMismatchedOperands(operands)
end
when "lrotatei", "lrotateq"
- riscv64RaiseUnsupported
+ riscv64WASMPlaceholder
when "rrotatei", "rrotateq"
- riscv64RaiseUnsupported
+ riscv64WASMPlaceholder
when "moved"
riscv64EmitFPOperation(operands, "fmv.d")
when "loadf"
@@ -2033,9 +2053,9 @@
when "cd2f"
riscv64EmitFPConvertOperation(operands, :d, :s, :none)
when "tzcnti", "tzcntq"
- riscv64RaiseUnsupported
+ riscv64WASMPlaceholder
when "lzcnti", "lzcntq"
- riscv64RaiseUnsupported
+ riscv64WASMPlaceholder
when "andf"
riscv64EmitFPBitwiseOperation(operands, :s, "and")
when "andd"
@@ -2057,7 +2077,7 @@
when "cfgteq"
riscv64EmitFPCompare(operands, :s, :gteq)
when "cfnequn"
- riscv64EmitFPCompare(operands, :s, :nequn)
+ riscv64WASMPlaceholder
when "cdeq"
riscv64EmitFPCompare(operands, :d, :eq)
when "cdneq"
@@ -2071,7 +2091,7 @@
when "cdgteq"
riscv64EmitFPCompare(operands, :d, :gteq)
when "cdnequn"
- riscv64EmitFPCompare(operands, :d, :nequn)
+ riscv64WASMPlaceholder
when "fi2f"
riscv64EmitFPCopy(operands, :s)
when "ff2i"
@@ -2083,9 +2103,9 @@
when "tls_loadp", "tls_storep"
riscv64RaiseUnsupported
when "loadlinkacqb", "loadlinkacqh", "loadlinkacqi", "loadlinkacqq"
- riscv64RaiseUnsupported
+ riscv64WASMPlaceholder
when "storecondrelb", "storecondrelh", "storecondreli", "storecondrelq"
- riscv64RaiseUnsupported
+ riscv64WASMPlaceholder
when "atomicxchgaddb", "atomicxchgaddh", "atomicxchgaddi", "atomicxchgaddq"
riscv64RaiseUnsupported
when "atomicxchgclearb", "atomicxchgclearh", "atomicxchgcleari", "atomicxchgclearq"
