Branch: refs/heads/main
Home: https://github.com/WebKit/WebKit
Commit: 1bb041b2af7af0a06a451fa6f1a536d453781647
https://github.com/WebKit/WebKit/commit/1bb041b2af7af0a06a451fa6f1a536d453781647
Author: Yijia Huang <hyjo...@gmail.com>
Date: 2022-12-08 (Thu, 08 Dec 2022)
Changed paths:
M Source/JavaScriptCore/assembler/MacroAssemblerX86_64.h
M Source/JavaScriptCore/assembler/X86Assembler.h
M Source/JavaScriptCore/b3/air/AirOpcode.opcodes
M Source/JavaScriptCore/wasm/WasmAirIRGenerator.cpp
Log Message:
-----------
[SIMD] Intel support for conversions
https://bugs.webkit.org/show_bug.cgi?id=248973
rdar://103144338
Reviewed by Yusuke Suzuki.
https://github.com/WebAssembly/simd/blob/main/proposals/simd/SIMD.md#conversions
Add support for conversion operations except for
```
f64x2.convert_low_i32x4_u(a: v128) -> v128
i32x4.trunc_sat_f32x4_s(a: v128) -> v128
i32x4.trunc_sat_f32x4_u(a: v128) -> v128
```
* Source/JavaScriptCore/assembler/MacroAssemblerX86Common.h:
(JSC::MacroAssemblerX86Common::supportsAVX):
* Source/JavaScriptCore/assembler/MacroAssemblerX86_64.h:
(JSC::MacroAssemblerX86_64::vectorTruncSat):
(JSC::MacroAssemblerX86_64::vectorSignedTruncSatF64):
(JSC::MacroAssemblerX86_64::vectorUnsignedTruncSatF64):
(JSC::MacroAssemblerX86_64::vectorExtendLow):
(JSC::MacroAssemblerX86_64::vectorExtendHigh):
(JSC::MacroAssemblerX86_64::vectorPromote):
(JSC::MacroAssemblerX86_64::vectorDemote):
(JSC::MacroAssemblerX86_64::vectorNarrow):
(JSC::MacroAssemblerX86_64::vectorConvert):
(JSC::MacroAssemblerX86_64::vectorConvertUnsigned):
(JSC::MacroAssemblerX86_64::vectorConvertLow):
* Source/JavaScriptCore/assembler/X86Assembler.h:
(JSC::X86Assembler::vunpcklps_rr):
(JSC::X86Assembler::vshufps_rr):
(JSC::X86Assembler::pxor_rr):
(JSC::X86Assembler::pblendw_rr):
(JSC::X86Assembler::vpmulhrsw_rr):
(JSC::X86Assembler::addps_rr):
(JSC::X86Assembler::psubd_rr):
(JSC::X86Assembler::cvtdq2ps_rr):
(JSC::X86Assembler::vcvtdq2ps_rr):
(JSC::X86Assembler::cvtdq2pd_rr):
(JSC::X86Assembler::vcvtdq2pd_rr):
(JSC::X86Assembler::vsubpd_rr):
(JSC::X86Assembler::vxorpd_rr):
(JSC::X86Assembler::vmaxpd_rr):
(JSC::X86Assembler::vminpd_rr):
(JSC::X86Assembler::vroundpd_rr):
(JSC::X86Assembler::vaddpd_rr):
(JSC::X86Assembler::vcmppd_rr):
(JSC::X86Assembler::vcmpeqpd_rr):
(JSC::X86Assembler::vcvttpd2dq_rr):
(JSC::X86Assembler::vandpd_rr):
(JSC::X86Assembler::vcvtpd2ps_rr):
(JSC::X86Assembler::vcvtps2pd_rr):
(JSC::X86Assembler::packsswb_rr):
(JSC::X86Assembler::vpacksswb_rr):
(JSC::X86Assembler::packuswb_rr):
(JSC::X86Assembler::vpackuswb_rr):
(JSC::X86Assembler::packssdw_rr):
(JSC::X86Assembler::vpackssdw_rr):
(JSC::X86Assembler::packusdw_rr):
(JSC::X86Assembler::vpackusdw_rr):
(JSC::X86Assembler::pmovsxbw):
(JSC::X86Assembler::vpmovsxbw):
(JSC::X86Assembler::pmovzxbw):
(JSC::X86Assembler::vpmovzxbw):
(JSC::X86Assembler::pmovsxwd):
(JSC::X86Assembler::vpmovsxwd):
(JSC::X86Assembler::pmovzxwd):
(JSC::X86Assembler::vpmovzxwd):
(JSC::X86Assembler::pmovsxdq):
(JSC::X86Assembler::vpmovsxdq):
(JSC::X86Assembler::pmovzxdq):
(JSC::X86Assembler::vpmovzxdq):
(JSC::X86Assembler::vupckhpd):
(JSC::X86Assembler::psrld_i8r):
(JSC::X86Assembler::X86InstructionFormatter::SingleInstructionBufferWriter::memoryModRM):
* Source/JavaScriptCore/b3/air/AirOpcode.opcodes:
* Source/JavaScriptCore/wasm/WasmAirIRGenerator.cpp:
(JSC::Wasm::AirIRGenerator::addSIMDV_V):
Canonical link: https://commits.webkit.org/257592@main
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