Branch: refs/heads/main
Home: https://github.com/WebKit/WebKit
Commit: 9610c2113b4510c465fe0cf6b5dd3cd0c5a2f7f7
https://github.com/WebKit/WebKit/commit/9610c2113b4510c465fe0cf6b5dd3cd0c5a2f7f7
Author: Sosuke Suzuki <[email protected]>
Date: 2026-07-29 (Wed, 29 Jul 2026)
Changed paths:
M Source/JavaScriptCore/offlineasm/arm64.rb
Log Message:
-----------
[JSC] offlineasm never emits ARM64 register-offset addressing for BaseIndex
operands
https://bugs.webkit.org/show_bug.cgi?id=320532
Reviewed by Yusuke Suzuki.
The ARM64 predicate passed to riscLowerMalformedAddresses compared
address.scale (an Immediate AST node) against Ruby integers, and
Immediate#== only returns true when the other side is also an Immediate.
So `address.scale == 1 or address.scale == size` was always false and
every BaseIndex load/store was lowered to `add tmp, base, index, lsl #n`
followed by `ldr/str [tmp]`, even though BaseIndex#arm64Operand can emit
`[base, index, lsl #n]` directly.
Compare address.scaleValue instead. Because the register-offset form now
actually reaches the emitters, keep lowering the address for opcodes whose
emitters only accept other address forms: load/store pair (`[base, #imm]`
via arm64PairAddressOperand), atomic/loadlinkacq/storecondrel (`[base]` via
arm64SimpleAddressOperand), loadv/storev (128-bit access, but the size
table says 8 and would produce an invalid `lsl #3`), loadqinc (post-index),
and non-ADDRESS64 configurations (unchanged behavior).
Before: add x13, x3, x4, lsl #3
ldr x5, [x13]
After: ldr x5, [x3, x4, lsl #3]
On macOS arm64 this removes 5,038 instructions (-6.4%) from LLIntAssembly.h.
* Source/JavaScriptCore/offlineasm/arm64.rb:
Canonical link: https://commits.webkit.org/318210@main
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