Title: [189036] branches/jsc-tailcall/Source/_javascript_Core
- Revision
- 189036
- Author
- msab...@apple.com
- Date
- 2015-08-27 10:54:29 -0700 (Thu, 27 Aug 2015)
Log Message
jsc-tailcall: Test failures with FTL enabled after r188986
https://bugs.webkit.org/show_bug.cgi?id=148494
Reviewed by Basile Clement.
During FTL OSR exit processing, we can't use a callee save register as a temp when
transferring the saved version of that registers from the FTL's stack location to the
baseline's stack location. If we do, we'll overwrite the tag registers that we
materialized previously.
* ftl/FTLOSRExitCompiler.cpp:
(JSC::FTL::compileStub):
Modified Paths
Diff
Modified: branches/jsc-tailcall/Source/_javascript_Core/ChangeLog (189035 => 189036)
--- branches/jsc-tailcall/Source/_javascript_Core/ChangeLog 2015-08-27 17:51:42 UTC (rev 189035)
+++ branches/jsc-tailcall/Source/_javascript_Core/ChangeLog 2015-08-27 17:54:29 UTC (rev 189036)
@@ -1,3 +1,18 @@
+2015-08-27 Michael Saboff <msab...@apple.com>
+
+ jsc-tailcall: Test failures with FTL enabled after r188986
+ https://bugs.webkit.org/show_bug.cgi?id=148494
+
+ Reviewed by Basile Clement.
+
+ During FTL OSR exit processing, we can't use a callee save register as a temp when
+ transferring the saved version of that registers from the FTL's stack location to the
+ baseline's stack location. If we do, we'll overwrite the tag registers that we
+ materialized previously.
+
+ * ftl/FTLOSRExitCompiler.cpp:
+ (JSC::FTL::compileStub):
+
2015-08-26 Michael Saboff <msab...@apple.com>
jsc-tailcall: Integrate FTL OSR entry / exit and exceptions handling of callee save registers with other tiers
Modified: branches/jsc-tailcall/Source/_javascript_Core/ftl/FTLOSRExitCompiler.cpp (189035 => 189036)
--- branches/jsc-tailcall/Source/_javascript_Core/ftl/FTLOSRExitCompiler.cpp 2015-08-27 17:51:42 UTC (rev 189035)
+++ branches/jsc-tailcall/Source/_javascript_Core/ftl/FTLOSRExitCompiler.cpp 2015-08-27 17:54:29 UTC (rev 189036)
@@ -440,22 +440,24 @@
unsigned unwindIndex = codeBlock->calleeSaveRegisters()->indexOf(reg);
RegisterAtOffset* baselineRegisterOffset = baselineCalleeSaves->find(reg);
+ GPRReg regToLoad = baselineRegisterOffset ? GPRInfo::regT0 : reg.gpr();
+
if (unwindIndex == UINT_MAX) {
// The FTL compilation didn't preserve this register. This means that it also
// didn't use the register. So its value at the beginning of OSR exit should be
// preserved by the thunk. Luckily, we saved all registers into the register
// scratch buffer, so we can restore them from there.
- jit.load64(registerScratch + offsetOfReg(reg), reg.gpr());
+ jit.load64(registerScratch + offsetOfReg(reg), regToLoad);
} else {
// The FTL compilation preserved the register. Its new value is therefore
// irrelevant, but we can get the value that was preserved by using the unwind
// data. We've already copied all unwind-able preserved registers into the unwind
// scratch buffer, so we can get it from there.
- jit.load64(unwindScratch + unwindIndex, reg.gpr());
+ jit.load64(unwindScratch + unwindIndex, regToLoad);
}
if (baselineRegisterOffset)
- jit.store64(reg.gpr(), MacroAssembler::Address(MacroAssembler::framePointerRegister, baselineRegisterOffset->offset()));
+ jit.store64(regToLoad, MacroAssembler::Address(MacroAssembler::framePointerRegister, baselineRegisterOffset->offset()));
}
size_t baselineVirtualRegistersForCalleeSaves = baselineCodeBlock->calleeSaveSpaceAsVirtualRegisters();
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