Title: [198953] trunk/Source/_javascript_Core
Revision
198953
Author
[email protected]
Date
2016-04-01 12:20:08 -0700 (Fri, 01 Apr 2016)

Log Message

[JSC][x86] Add the 3 operands form of floating point substraction
https://bugs.webkit.org/show_bug.cgi?id=156095

Patch by Benjamin Poulain <[email protected]> on 2016-04-01
Reviewed by Geoffrey Garen.

Same old, same old. Add the AVX form of subsd and subss.

Unfortunately, we cannot benefit from the 3 register form
in B3 yet because the Air script does not support CPU flags yet.
That can be fixed later.

* assembler/MacroAssemblerX86Common.h:
(JSC::MacroAssemblerX86Common::subDouble):
(JSC::MacroAssemblerX86Common::subFloat):
* assembler/X86Assembler.h:
(JSC::X86Assembler::vsubsd_rr):
(JSC::X86Assembler::subsd_mr):
(JSC::X86Assembler::vsubsd_mr):
(JSC::X86Assembler::vsubss_rr):
(JSC::X86Assembler::subss_mr):
(JSC::X86Assembler::vsubss_mr):
(JSC::X86Assembler::X86InstructionFormatter::SingleInstructionBufferWriter::memoryModRM):
* b3/air/AirOpcode.opcodes:

Modified Paths

Diff

Modified: trunk/Source/_javascript_Core/ChangeLog (198952 => 198953)


--- trunk/Source/_javascript_Core/ChangeLog	2016-04-01 19:15:05 UTC (rev 198952)
+++ trunk/Source/_javascript_Core/ChangeLog	2016-04-01 19:20:08 UTC (rev 198953)
@@ -1,3 +1,29 @@
+2016-04-01  Benjamin Poulain  <[email protected]>
+
+        [JSC][x86] Add the 3 operands form of floating point substraction
+        https://bugs.webkit.org/show_bug.cgi?id=156095
+
+        Reviewed by Geoffrey Garen.
+
+        Same old, same old. Add the AVX form of subsd and subss.
+
+        Unfortunately, we cannot benefit from the 3 register form
+        in B3 yet because the Air script does not support CPU flags yet.
+        That can be fixed later.
+
+        * assembler/MacroAssemblerX86Common.h:
+        (JSC::MacroAssemblerX86Common::subDouble):
+        (JSC::MacroAssemblerX86Common::subFloat):
+        * assembler/X86Assembler.h:
+        (JSC::X86Assembler::vsubsd_rr):
+        (JSC::X86Assembler::subsd_mr):
+        (JSC::X86Assembler::vsubsd_mr):
+        (JSC::X86Assembler::vsubss_rr):
+        (JSC::X86Assembler::subss_mr):
+        (JSC::X86Assembler::vsubss_mr):
+        (JSC::X86Assembler::X86InstructionFormatter::SingleInstructionBufferWriter::memoryModRM):
+        * b3/air/AirOpcode.opcodes:
+
 2016-04-01  Alberto Garcia  <[email protected]>
 
         [JSC] Missing PATH_MAX definition

Modified: trunk/Source/_javascript_Core/assembler/MacroAssemblerX86Common.h (198952 => 198953)


--- trunk/Source/_javascript_Core/assembler/MacroAssemblerX86Common.h	2016-04-01 19:15:05 UTC (rev 198952)
+++ trunk/Source/_javascript_Core/assembler/MacroAssemblerX86Common.h	2016-04-01 19:20:08 UTC (rev 198953)
@@ -1245,35 +1245,89 @@
 
     void subDouble(FPRegisterID src, FPRegisterID dest)
     {
-        ASSERT(isSSE2Present());
-        m_assembler.subsd_rr(src, dest);
+        subDouble(dest, src, dest);
     }
 
     void subDouble(FPRegisterID op1, FPRegisterID op2, FPRegisterID dest)
     {
-        // B := A - B is invalid.
-        ASSERT(op1 == dest || op2 != dest);
+        if (supportsAVX())
+            m_assembler.vsubsd_rr(op1, op2, dest);
+        else {
+            ASSERT(isSSE2Present());
 
-        moveDouble(op1, dest);
-        subDouble(op2, dest);
+            // B := A - B is invalid.
+            ASSERT(op1 == dest || op2 != dest);
+            moveDouble(op1, dest);
+            m_assembler.subsd_rr(op2, dest);
+        }
     }
 
+    void subDouble(FPRegisterID op1, Address op2, FPRegisterID dest)
+    {
+        if (supportsAVX())
+            m_assembler.vsubsd_mr(op1, op2.offset, op2.base, dest);
+        else {
+            moveDouble(op1, dest);
+            m_assembler.subsd_mr(op2.offset, op2.base, dest);
+        }
+    }
+
+    void subDouble(FPRegisterID op1, BaseIndex op2, FPRegisterID dest)
+    {
+        if (supportsAVX())
+            m_assembler.vsubsd_mr(op1, op2.offset, op2.base, op2.index, op2.scale, dest);
+        else {
+            moveDouble(op1, dest);
+            m_assembler.subsd_mr(op2.offset, op2.base, op2.index, op2.scale, dest);
+        }
+    }
+
     void subDouble(Address src, FPRegisterID dest)
     {
-        ASSERT(isSSE2Present());
-        m_assembler.subsd_mr(src.offset, src.base, dest);
+        subDouble(dest, src, dest);
     }
 
     void subFloat(FPRegisterID src, FPRegisterID dest)
     {
-        ASSERT(isSSE2Present());
-        m_assembler.subss_rr(src, dest);
+        subFloat(dest, src, dest);
     }
 
+    void subFloat(FPRegisterID op1, FPRegisterID op2, FPRegisterID dest)
+    {
+        if (supportsAVX())
+            m_assembler.vsubss_rr(op1, op2, dest);
+        else {
+            ASSERT(isSSE2Present());
+            // B := A - B is invalid.
+            ASSERT(op1 == dest || op2 != dest);
+            moveDouble(op1, dest);
+            m_assembler.subss_rr(op2, dest);
+        }
+    }
+
+    void subFloat(FPRegisterID op1, Address op2, FPRegisterID dest)
+    {
+        if (supportsAVX())
+            m_assembler.vsubss_mr(op1, op2.offset, op2.base, dest);
+        else {
+            moveDouble(op1, dest);
+            m_assembler.subss_mr(op2.offset, op2.base, dest);
+        }
+    }
+
+    void subFloat(FPRegisterID op1, BaseIndex op2, FPRegisterID dest)
+    {
+        if (supportsAVX())
+            m_assembler.vsubss_mr(op1, op2.offset, op2.base, op2.index, op2.scale, dest);
+        else {
+            moveDouble(op1, dest);
+            m_assembler.subss_mr(op2.offset, op2.base, op2.index, op2.scale, dest);
+        }
+    }
+
     void subFloat(Address src, FPRegisterID dest)
     {
-        ASSERT(isSSE2Present());
-        m_assembler.subss_mr(src.offset, src.base, dest);
+        subFloat(dest, src, dest);
     }
 
     void mulDouble(FPRegisterID src, FPRegisterID dest)

Modified: trunk/Source/_javascript_Core/assembler/X86Assembler.h (198952 => 198953)


--- trunk/Source/_javascript_Core/assembler/X86Assembler.h	2016-04-01 19:15:05 UTC (rev 198952)
+++ trunk/Source/_javascript_Core/assembler/X86Assembler.h	2016-04-01 19:20:08 UTC (rev 198953)
@@ -2441,24 +2441,66 @@
         m_formatter.twoByteOp(OP2_SUBSD_VsdWsd, (RegisterID)dst, (RegisterID)src);
     }
 
+    void vsubsd_rr(XMMRegisterID a, XMMRegisterID b, XMMRegisterID dst)
+    {
+        m_formatter.vexNdsLigWigTwoByteOp(PRE_SSE_F2, OP2_SUBSD_VsdWsd, (RegisterID)dst, (RegisterID)a, (RegisterID)b);
+    }
+
     void subsd_mr(int offset, RegisterID base, XMMRegisterID dst)
     {
         m_formatter.prefix(PRE_SSE_F2);
         m_formatter.twoByteOp(OP2_SUBSD_VsdWsd, (RegisterID)dst, base, offset);
     }
 
+    void subsd_mr(int offset, RegisterID base, RegisterID index, int scale, XMMRegisterID dst)
+    {
+        m_formatter.prefix(PRE_SSE_F2);
+        m_formatter.twoByteOp(OP2_SUBSD_VsdWsd, dst, base, index, scale, offset);
+    }
+
+    void vsubsd_mr(XMMRegisterID b, int offset, RegisterID base, XMMRegisterID dst)
+    {
+        m_formatter.vexNdsLigWigTwoByteOp(PRE_SSE_F2, OP2_SUBSD_VsdWsd, (RegisterID)dst, (RegisterID)b, base, offset);
+    }
+
+    void vsubsd_mr(XMMRegisterID b, int offset, RegisterID base, RegisterID index, int scale, XMMRegisterID dst)
+    {
+        m_formatter.vexNdsLigWigTwoByteOp(PRE_SSE_F2, OP2_SUBSD_VsdWsd, (RegisterID)dst, (RegisterID)b, offset, base, index, scale);
+    }
+
     void subss_rr(XMMRegisterID src, XMMRegisterID dst)
     {
         m_formatter.prefix(PRE_SSE_F3);
         m_formatter.twoByteOp(OP2_SUBSD_VsdWsd, (RegisterID)dst, (RegisterID)src);
     }
 
+    void vsubss_rr(XMMRegisterID a, XMMRegisterID b, XMMRegisterID dst)
+    {
+        m_formatter.vexNdsLigWigTwoByteOp(PRE_SSE_F3, OP2_SUBSD_VsdWsd, (RegisterID)dst, (RegisterID)a, (RegisterID)b);
+    }
+
     void subss_mr(int offset, RegisterID base, XMMRegisterID dst)
     {
         m_formatter.prefix(PRE_SSE_F3);
         m_formatter.twoByteOp(OP2_SUBSD_VsdWsd, (RegisterID)dst, base, offset);
     }
 
+    void subss_mr(int offset, RegisterID base, RegisterID index, int scale, XMMRegisterID dst)
+    {
+        m_formatter.prefix(PRE_SSE_F3);
+        m_formatter.twoByteOp(OP2_SUBSD_VsdWsd, dst, base, index, scale, offset);
+    }
+
+    void vsubss_mr(XMMRegisterID b, int offset, RegisterID base, XMMRegisterID dst)
+    {
+        m_formatter.vexNdsLigWigTwoByteOp(PRE_SSE_F3, OP2_SUBSD_VsdWsd, (RegisterID)dst, (RegisterID)b, base, offset);
+    }
+
+    void vsubss_mr(XMMRegisterID b, int offset, RegisterID base, RegisterID index, int scale, XMMRegisterID dst)
+    {
+        m_formatter.vexNdsLigWigTwoByteOp(PRE_SSE_F3, OP2_SUBSD_VsdWsd, (RegisterID)dst, (RegisterID)b, offset, base, index, scale);
+    }
+
     void ucomisd_rr(XMMRegisterID src, XMMRegisterID dst)
     {
         m_formatter.prefix(PRE_SSE_66);
@@ -3339,15 +3381,10 @@
             writer.memoryModRM(reg, address);
         }
 #endif
-        void vexNdsLigWigCommutativeTwoByteOp(OneByteOpcodeID simdPrefix, TwoByteOpcodeID opcode, RegisterID dest, RegisterID a, RegisterID b)
+        void vexNdsLigWigTwoByteOp(OneByteOpcodeID simdPrefix, TwoByteOpcodeID opcode, RegisterID dest, RegisterID a, RegisterID b)
         {
             SingleInstructionBufferWriter writer(m_buffer);
-
-            // Since this is a commutative operation, we can try switching the arguments.
             if (regRequiresRex(b))
-                std::swap(a, b);
-
-            if (regRequiresRex(b))
                 writer.threeBytesVexNds(simdPrefix, VexImpliedBytes::TwoBytesOp, dest, a, b);
             else
                 writer.twoBytesVex(simdPrefix, a, dest);
@@ -3355,6 +3392,14 @@
             writer.registerModRM(dest, b);
         }
 
+        void vexNdsLigWigCommutativeTwoByteOp(OneByteOpcodeID simdPrefix, TwoByteOpcodeID opcode, RegisterID dest, RegisterID a, RegisterID b)
+        {
+            // Since this is a commutative operation, we can try switching the arguments.
+            if (regRequiresRex(b))
+                std::swap(a, b);
+            vexNdsLigWigTwoByteOp(simdPrefix, opcode, dest, a, b);
+        }
+
         void vexNdsLigWigTwoByteOp(OneByteOpcodeID simdPrefix, TwoByteOpcodeID opcode, RegisterID dest, RegisterID a, RegisterID base, int offset)
         {
             SingleInstructionBufferWriter writer(m_buffer);

Modified: trunk/Source/_javascript_Core/b3/air/AirOpcode.opcodes (198952 => 198953)


--- trunk/Source/_javascript_Core/b3/air/AirOpcode.opcodes	2016-04-01 19:15:05 UTC (rev 198952)
+++ trunk/Source/_javascript_Core/b3/air/AirOpcode.opcodes	2016-04-01 19:20:08 UTC (rev 198953)
@@ -177,15 +177,19 @@
     x86: Addr, Tmp
     x86: Tmp, Addr
 
-arm64: SubDouble U:F:64, U:F:64, D:F:64
-    Tmp, Tmp, Tmp
+SubDouble U:F:64, U:F:64, D:F:64
+    arm64: Tmp, Tmp, Tmp
+    x86: Tmp, Addr, Tmp
+    x86: Tmp, Index, Tmp
 
 x86: SubDouble U:F:64, UD:F:64
     Tmp, Tmp
     Addr, Tmp
 
-arm64: SubFloat U:F:32, U:F:32, D:F:32
-    Tmp, Tmp, Tmp
+SubFloat U:F:32, U:F:32, D:F:32
+    arm64: Tmp, Tmp, Tmp
+    x86: Tmp, Addr, Tmp
+    x86: Tmp, Index, Tmp
 
 x86: SubFloat U:F:32, UD:F:32
     Tmp, Tmp
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