Hi all, I've been doing some thinking about where processor architecture are headed, and the programming models required. It seem clear to me that neither shared mutable memory, nor cache coherency can scale up to hundreds of cores. Hence future processors will have to look very similar to today's GPUs, or some hybrid thing like the Cell. Intel is going in the same direction with Larrabee, although I believe that its use of cache coherency won't survive for very long, probably not above the 100 cores mark.
It seems like the future architectures will need to include both: - memory partitioned across cores - programmer-controlled cache X10 is ideally equipped for the former thanks to PGAS. How about the latter? Is there any ongoing work on a Cell or GPU runtime for X10? I think a truly future-proof language, at this point, should enable good performance for the same program on all of Cell, GPUs, single-chip multicore CPU, and clusters. As an aside, has explicit message passing been considered in X10 for communication between places? I suppose futures are an equivalent primitive but I'm partial to message passing as in the actor model, and to the join calculus (although I don't know if it can be implemented efficiently across a cluster of machines). Feel free to point at my mistakes or redirect the conversation to another list if appropriate. Cheers, -- Olivier Pernet We are the knights who say echo '16i[q]sa[ln0=aln100%Pln100/snlbx]sbA0D4D465452snlbxq'|dc ------------------------------------------------------------------------------ Stay on top of everything new and different, both inside and around Java (TM) technology - register by April 22, and save $200 on the JavaOne (SM) conference, June 2-5, 2009, San Francisco. 300 plus technical and hands-on sessions. Register today. Use priority code J9JMT32. http://p.sf.net/sfu/p _______________________________________________ X10-users mailing list [email protected] https://lists.sourceforge.net/lists/listinfo/x10-users
