# HG changeset patch # User Murugan Vairavel <[email protected]> # Date 1384256194 -19800 # Tue Nov 12 17:06:34 2013 +0530 # Node ID 7a8118d07276312b2971b292d689805074abd28a # Parent 85749f42e3fa7c03ce29903d1457dc0ed873c120 asm: pixelsub_ps routine for 2xN block sizes (Modified)
diff -r 85749f42e3fa -r 7a8118d07276 source/common/x86/pixel-a.asm --- a/source/common/x86/pixel-a.asm Tue Nov 12 03:16:45 2013 +0530 +++ b/source/common/x86/pixel-a.asm Tue Nov 12 17:06:34 2013 +0530 @@ -5288,97 +5288,244 @@ ;----------------------------------------------------------------------------- ; void pixel_sub_ps_c_2x4(int16_t *dest, intptr_t destride, pixel *src0, pixel *src1, intptr_t srcstride0, intptr_t srcstride1); ;----------------------------------------------------------------------------- -INIT_XMM sse4 -cglobal pixel_sub_ps_2x4, 6, 6, 4, dest, deststride, src0, src1, srcstride0, srcstride1 - -add r1, r1 - -movd m0, [r2] -pinsrw m0, [r2 + r4], 2 -movd m1, [r2 + 2 * r4] - -movd m2, [r3] -pinsrw m2, [r3 + r5], 2 -movd m3, [r3 + 2 * r5] - -lea r2, [r2 + 2 * r4] -lea r3, [r3 + 2 * r5] - -pinsrw m1, [r2 + r4], 2 -pinsrw m3, [r3 + r5], 2 - -pmovzxbw m0, m0 -pmovzxbw m1, m1 -pmovzxbw m2, m2 -pmovzxbw m3, m3 - -psubw m0, m2 -psubw m1, m3 - -movd [r0], m0 -pextrd [r0 + r1], m0, 2 -movd [r0 + 2* r1], m1 - -lea r0, [r0 + 2 * r1] - -pextrd [r0 + r1], m1, 2 - +INIT_XMM sse4 +%if ARCH_X86_64 + cglobal pixel_sub_ps_2x4, 6, 8, 0 + + %define tmp_r1 r1 + DECLARE_REG_TMP 6, 7 +%else + cglobal pixel_sub_ps_2x4, 6, 7, 0, 0-4 + + %define tmp_r1 dword [rsp] + DECLARE_REG_TMP 6, 1 +%endif ; ARCH_X86_64 + + add r1, r1 + +%if ARCH_X86_64 == 0 + mov tmp_r1, r1 + +%endif + +movzx t0d, byte [r2] +movzx t1d, byte [r3] + +sub t0d, t1d + +mov [r0], t0w + +movzx t0d, byte [r2 + 1] +movzx t1d, byte [r3 + 1] + +sub t0d, t1d + +mov [r0 + 2], t0w + +add r0, tmp_r1 + +movzx t0d, byte [r2 + r4] +movzx t1d, byte [r3 + r5] + +sub t0d, t1d + +mov [r0], t0w + +movzx t0d, byte [r2 + r4 + 1] +movzx t1d, byte [r3 + r5 + 1] + +sub t0d, t1d + +mov [r0 + 2], t0w + +add r0, tmp_r1 + +movzx t0d, byte [r2 + r4 * 2] +movzx t1d, byte [r3 + r5 * 2] + +sub t0d, t1d + +mov [r0], t0w + +movzx t0d, byte [r2 + r4 * 2 + 1] +movzx t1d, byte [r3 + r5 * 2 + 1] + +sub t0d, t1d + +mov [r0 + 2], t0w + +add r0, tmp_r1 + +lea r2, [r2 + r4 * 2] +lea r3, [r3 + r5 * 2] + +movzx t0d, byte [r2 + r4] +movzx t1d, byte [r3 + r5] + +sub t0d, t1d + +mov [r0], t0w + +movzx t0d, byte [r2 + r4 + 1] +movzx t1d, byte [r3 + r5 + 1] + +sub t0d, t1d + +mov [r0 + 2], t0w + RET ;----------------------------------------------------------------------------- -; void pixel_sub_ps_c_%1x%2(int16_t *dest, intptr_t destride, pixel *src0, pixel *src1, intptr_t srcstride0, intptr_t srcstride1); +; void pixel_sub_ps_c_2x8(pixel *dest, intptr_t destride, pixel *src0, pixel *src1, intptr_t srcstride0, intptr_t srcstride1); ;----------------------------------------------------------------------------- -%macro PIXELSUB_PS_W2_H4 2 -INIT_XMM sse4 -cglobal pixel_sub_ps_%1x%2, 6, 7, 4, dest, deststride, src0, src1, srcstride0, srcstride1 - -add r1, r1 -mov r6d, %2/4 - -.loop - - movd m0, [r2] - pinsrw m0, [r2 + r4], 2 - movd m1, [r2 + 2 * r4] - - movd m2, [r3] - pinsrw m2, [r3 + r5], 2 - movd m3, [r3 + 2 * r5] - - lea r2, [r2 + 2 * r4] - lea r3, [r3 + 2 * r5] - - pinsrw m1, [r2 + r4], 2 - pinsrw m3, [r3 + r5], 2 - - pmovzxbw m0, m0 - pmovzxbw m1, m1 - pmovzxbw m2, m2 - pmovzxbw m3, m3 - - psubw m0, m2 - psubw m1, m3 - - movd [r0], m0 - pextrd [r0 + r1], m0, 2 - movd [r0 + 2* r1], m1 - - lea r0, [r0 + 2 * r1] - - pextrd [r0 + r1], m1, 2 - - lea r2, [r2 + 2 * r4] - lea r3, [r3 + 2 * r5] - lea r0, [r0 + 2 * r1] - - dec r6d - -jnz .loop +INIT_XMM sse4 +%if ARCH_X86_64 + cglobal pixel_sub_ps_2x8, 6, 8, 0 + + %define tmp_r1 r1 + DECLARE_REG_TMP 6, 7 +%else + cglobal pixel_sub_ps_2x8, 6, 7, 0, 0-4 + + %define tmp_r1 dword [rsp] + DECLARE_REG_TMP 6, 1 +%endif ; ARCH_X86_64 + + add r1, r1 + +%if ARCH_X86_64 == 0 + mov tmp_r1, r1 + +%endif + + movzx t0d, byte [r2] + movzx t1d, byte [r3] + + sub t0d, t1d + + mov [r0], t0w + movzx t0d, byte [r2 + 1] + movzx t1d, byte [r3 + 1] + + sub t0d, t1d + + mov [r0 + 2], t0w + + add r0, tmp_r1 + + movzx t0d, byte [r2 + r4] + movzx t1d, byte [r3 + r5] + + sub t0d, t1d + + mov [r0], t0w + movzx t0d, byte [r2 + r4 + 1] + movzx t1d, byte [r3 + r5 + 1] + + sub t0d, t1d + + mov [r0 + 2], t0w + + add r0, tmp_r1 + + movzx t0d, byte [r2 + r4 * 2] + movzx t1d, byte [r3 + r5 * 2] + + sub t0d, t1d + + mov [r0], t0w + movzx t0d, byte [r2 + r4 * 2 + 1] + movzx t1d, byte [r3 + r5 * 2 + 1] + + sub t0d, t1d + + mov [r0 + 2], t0w + + add r0, tmp_r1 + + lea r2, [r2 + r4 * 2] + lea r3, [r3 + r5 * 2] + + movzx t0d, byte [r2 + r4] + movzx t1d, byte [r3 + r5] + + sub t0d, t1d + + mov [r0], t0w + movzx t0d, byte [r2 + r4 + 1] + movzx t1d, byte [r3 + r5 + 1] + + sub t0d, t1d + + mov [r0 + 2], t0w + + add r0, tmp_r1 + + movzx t0d, byte [r2 + r4 * 2] + movzx t1d, byte [r3 + r5 * 2] + + sub t0d, t1d + + mov [r0], t0w + movzx t0d, byte [r2 + r4 * 2 + 1] + movzx t1d, byte [r3 + r5 * 2 + 1] + + sub t0d, t1d + + mov [r0 + 2], t0w + + add r0, tmp_r1 + + lea r2, [r2 + r4 * 2] + lea r3, [r3 + r5 * 2] + + movzx t0d, byte [r2 + r4] + movzx t1d, byte [r3 + r5] + + sub t0d, t1d + + mov [r0], t0w + movzx t0d, byte [r2 + r4 + 1] + movzx t1d, byte [r3 + r5 + 1] + + sub t0d, t1d + + mov [r0 + 2], t0w + + add r0, tmp_r1 + + movzx t0d, byte [r2 + r4 * 2] + movzx t1d, byte [r3 + r5 * 2] + + sub t0d, t1d + + mov [r0], t0w + movzx t0d, byte [r2 + r4 * 2 + 1] + movzx t1d, byte [r3 + r5 * 2 + 1] + + sub t0d, t1d + + mov [r0 + 2], t0w + + add r0, tmp_r1 + + lea r2, [r2 + r4 * 2] + lea r3, [r3 + r5 * 2] + + movzx t0d, byte [r2 + r4] + movzx t1d, byte [r3 + r5] + + sub t0d, t1d + + mov [r0], t0w + movzx t0d, byte [r2 + r4 + 1] + movzx t1d, byte [r3 + r5 + 1] + + sub t0d, t1d + + mov [r0 + 2], t0w RET -%endmacro - -PIXELSUB_PS_W2_H4 2, 8 ;----------------------------------------------------------------------------- ; void pixel_sub_sp_c_4x2(int16_t *dest, intptr_t destride, pixel *src0, pixel *src1, intptr_t srcstride0, intptr_t srcstride1); _______________________________________________ x265-devel mailing list [email protected] https://mailman.videolan.org/listinfo/x265-devel
