# HG changeset patch
# User Praveen Tiwari <prav...@multicorewareinc.com>
# Date 1426577763 -19800
# Node ID 109d1caf0fe85359ce096e00bf841928800139ec
# Parent ca0a4b2c53c54431a3b8471bbf4dadf6ee62c8c5
asm-intra_pred_ang16_24: improved speedup by ~40 over SSE4
AVX2:
intra_ang_16x16[24] 20.38x 409.84 8352.03
SSE4:
intra_ang_16x16[24] 12.24x 684.46 8380.80
diff -r ca0a4b2c53c5 -r 109d1caf0fe8 source/common/x86/asm-primitives.cpp
--- a/source/common/x86/asm-primitives.cpp Wed Mar 18 08:09:12 2015 +0530
+++ b/source/common/x86/asm-primitives.cpp Tue Mar 17 13:06:03 2015 +0530
@@ -1527,6 +1527,7 @@
p.cu[BLOCK_16x16].intra_pred[31] = x265_intra_pred_ang16_31_avx2;
p.cu[BLOCK_16x16].intra_pred[32] = x265_intra_pred_ang16_32_avx2;
p.cu[BLOCK_16x16].intra_pred[33] = x265_intra_pred_ang16_33_avx2;
+ p.cu[BLOCK_16x16].intra_pred[24] = x265_intra_pred_ang16_24_avx2;
// copy_sp primitives
p.cu[BLOCK_16x16].copy_sp = x265_blockcopy_sp_16x16_avx2;
diff -r ca0a4b2c53c5 -r 109d1caf0fe8 source/common/x86/intrapred.h
--- a/source/common/x86/intrapred.h Wed Mar 18 08:09:12 2015 +0530
+++ b/source/common/x86/intrapred.h Tue Mar 17 13:06:03 2015 +0530
@@ -191,6 +191,7 @@
void x265_intra_pred_ang16_31_avx2(pixel* dst, intptr_t dstStride, const
pixel* srcPix, int dirMode, int bFilter);
void x265_intra_pred_ang16_32_avx2(pixel* dst, intptr_t dstStride, const
pixel* srcPix, int dirMode, int bFilter);
void x265_intra_pred_ang16_33_avx2(pixel* dst, intptr_t dstStride, const
pixel* srcPix, int dirMode, int bFilter);
+void x265_intra_pred_ang16_24_avx2(pixel* dst, intptr_t dstStride, const
pixel* srcPix, int dirMode, int bFilter);
void x265_all_angs_pred_4x4_sse4(pixel *dest, pixel *refPix, pixel *filtPix,
int bLuma);
void x265_all_angs_pred_8x8_sse4(pixel *dest, pixel *refPix, pixel *filtPix,
int bLuma);
void x265_all_angs_pred_16x16_sse4(pixel *dest, pixel *refPix, pixel *filtPix,
int bLuma);
diff -r ca0a4b2c53c5 -r 109d1caf0fe8 source/common/x86/intrapred8.asm
--- a/source/common/x86/intrapred8.asm Wed Mar 18 08:09:12 2015 +0530
+++ b/source/common/x86/intrapred8.asm Tue Mar 17 13:06:03 2015 +0530
@@ -215,6 +215,16 @@
db 26, 6, 26, 6, 26, 6, 26, 6, 26, 6, 26, 6, 26, 6, 26,
6, 26, 6, 26, 6, 26, 6, 26, 6, 26, 6, 26, 6, 26, 6, 26, 6
db 32, 0, 32, 0, 32, 0, 32, 0, 32, 0, 32, 0, 32, 0, 32,
0, 32, 0, 32, 0, 32, 0, 32, 0, 32, 0, 32, 0, 32, 0, 32, 0
+ALIGN 32
+c_ang16_mode_24: db 5, 27, 5, 27, 5, 27, 5, 27, 5, 27, 5, 27, 5, 27, 5,
27, 10, 22, 10, 22, 10, 22, 10, 22, 10, 22, 10, 22, 10, 22, 10, 22
+ db 15, 17, 15, 17, 15, 17, 15, 17, 15, 17, 15, 17, 15,
17, 15, 17, 20, 12, 20, 12, 20, 12, 20, 12, 20, 12, 20, 12, 20, 12, 20, 12
+ db 25, 7, 25, 7, 25, 7, 25, 7, 25, 7, 25, 7, 25, 7, 25,
7, 30, 2, 30, 2, 30, 2, 30, 2, 30, 2, 30, 2, 30, 2, 30, 2
+ db 3, 29, 3, 29, 3, 29, 3, 29, 3, 29, 3, 29, 3, 29, 3,
29, 8, 24, 8, 24, 8, 24, 8, 24, 8, 24, 8, 24, 8, 24, 8, 24
+ db 13, 19, 13, 19, 13, 19, 13, 19, 13, 19, 13, 19, 13,
19, 13, 19, 18, 14, 18, 14, 18, 14, 18, 14, 18, 14, 18, 14, 18, 14, 18, 14
+ db 23, 9, 23, 9, 23, 9, 23, 9, 23, 9, 23, 9, 23, 9, 23,
9, 28, 4, 28, 4, 28, 4, 28, 4, 28, 4, 28, 4, 28, 4, 28, 4
+ db 1, 31, 1, 31, 1, 31, 1, 31, 1, 31, 1, 31, 1, 31, 1,
31, 6, 26, 6, 26, 6, 26, 6, 26, 6, 26, 6, 26, 6, 26, 6, 26
+ db 11, 21, 11, 21, 11, 21, 11, 21, 11, 21, 11, 21, 11,
21, 11, 21, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16
+
ALIGN 32
;; (blkSize - 1 - x)
pw_planar4_0: dw 3, 2, 1, 0, 3, 2, 1, 0
@@ -11134,3 +11144,42 @@
INTRA_PRED_ANG16_MC2 14
INTRA_PRED_ANG16_MC3 r0 + r3, 1
RET
+
+INIT_YMM avx2
+cglobal intra_pred_ang16_24, 3, 5, 6
+ mova m0, [pw_1024]
+ mova m5, [intra_pred_shuff_0_8]
+ lea r3, [3 * r1]
+ lea r4, [c_ang16_mode_24]
+
+ INTRA_PRED_ANG16_MC2 0
+ INTRA_PRED_ANG16_MC1 0
+
+ lea r0, [r0 + 4 * r1]
+ INTRA_PRED_ANG16_MC0 r0, r0 + r1, 2
+
+ movu xm1, [r2 - 1]
+ pinsrb xm1, [r2 + 38], 0
+ vinserti128 m1, m1, xm1, 1
+ pshufb m1, m5
+ vbroadcasti128 m2, [r2 + 7]
+ pshufb m2, m5
+ INTRA_PRED_ANG16_MC0 r0 + 2 * r1, r0 + r3, 3
+
+ lea r0, [r0 + 4 * r1]
+ add r4, 4 * mmsize
+
+ INTRA_PRED_ANG16_MC1 0
+
+ movu xm1, [r2 - 2]
+ pinsrb xm1, [r2 + 45], 0
+ pinsrb xm1, [r2 + 38], 1
+ vinserti128 m1, m1, xm1, 1
+ pshufb m1, m5
+ vbroadcasti128 m2, [r2 + 6]
+ pshufb m2, m5
+
+ lea r0, [r0 + 4 * r1]
+
+ INTRA_PRED_ANG16_MC1 2
+ RET
_______________________________________________
x265-devel mailing list
x265-devel@videolan.org
https://mailman.videolan.org/listinfo/x265-devel
