# HG changeset patch # User Vignesh Vijayakumar<vign...@multicorewareinc.com> # Date 1510735444 -19800 # Wed Nov 15 14:14:04 2017 +0530 # Node ID 06da2926583d766da027e141ed6c9cf2f77a208d # Parent 487307659c367f26096d0da0c81a89ca89b2ffbe x86: AVX512 interp_4tap_vert_sp_16xN and interp_4tap_vert_ss_16xN for high bit depth
i444 chroma_vsp Size | AVX2 performance | AVX512 performance ---------------------------------------------- 16x4 | 21.82x | 33.15x 16x8 | 22.65x | 32.41x 16x12 | 23.56x | 32.00x 16x16 | 24.08x | 34.31x 16x32 | 23.28x | 35.39x 16x64 | 24.43x | 36.54x i444 chroma_vss Size | AVX2 performance | AVX512 performance ---------------------------------------------- 16x4 | 19.90x | 30.10x 16x8 | 22.65x | 30.27x 16x12 | 24.85x | 30.14x 16x16 | 25.33x | 31.05x 16x32 | 25.08x | 35.79x 16x64 | 26.20x | 36.01x diff -r 487307659c36 -r 06da2926583d source/common/x86/asm-primitives.cpp --- a/source/common/x86/asm-primitives.cpp Tue Nov 14 19:16:49 2017 +0530 +++ b/source/common/x86/asm-primitives.cpp Wed Nov 15 14:14:04 2017 +0530 @@ -2677,6 +2677,7 @@ p.chroma[X265_CSP_I444].pu[LUMA_32x24].filter_vsp = PFX(interp_4tap_vert_sp_32x24_avx512); p.chroma[X265_CSP_I444].pu[LUMA_32x32].filter_vsp = PFX(interp_4tap_vert_sp_32x32_avx512); p.chroma[X265_CSP_I444].pu[LUMA_32x64].filter_vsp = PFX(interp_4tap_vert_sp_32x64_avx512); + p.chroma[X265_CSP_I444].pu[LUMA_16x4].filter_vpp = PFX(interp_4tap_vert_pp_16x4_avx512); p.chroma[X265_CSP_I444].pu[LUMA_16x8].filter_vpp = PFX(interp_4tap_vert_pp_16x8_avx512); p.chroma[X265_CSP_I444].pu[LUMA_16x12].filter_vpp = PFX(interp_4tap_vert_pp_16x12_avx512); @@ -2689,6 +2690,19 @@ p.chroma[X265_CSP_I444].pu[LUMA_16x16].filter_vps = PFX(interp_4tap_vert_ps_16x16_avx512); p.chroma[X265_CSP_I444].pu[LUMA_16x32].filter_vps = PFX(interp_4tap_vert_ps_16x32_avx512); p.chroma[X265_CSP_I444].pu[LUMA_16x64].filter_vps = PFX(interp_4tap_vert_ps_16x64_avx512); + p.chroma[X265_CSP_I444].pu[LUMA_16x4].filter_vss = PFX(interp_4tap_vert_ss_16x4_avx512); + p.chroma[X265_CSP_I444].pu[LUMA_16x8].filter_vss = PFX(interp_4tap_vert_ss_16x8_avx512); + p.chroma[X265_CSP_I444].pu[LUMA_16x12].filter_vss = PFX(interp_4tap_vert_ss_16x12_avx512); + p.chroma[X265_CSP_I444].pu[LUMA_16x16].filter_vss = PFX(interp_4tap_vert_ss_16x16_avx512); + p.chroma[X265_CSP_I444].pu[LUMA_16x32].filter_vss = PFX(interp_4tap_vert_ss_16x32_avx512); + p.chroma[X265_CSP_I444].pu[LUMA_16x64].filter_vss = PFX(interp_4tap_vert_ss_16x64_avx512); + p.chroma[X265_CSP_I444].pu[LUMA_16x4].filter_vsp = PFX(interp_4tap_vert_sp_16x4_avx512); + p.chroma[X265_CSP_I444].pu[LUMA_16x8].filter_vsp = PFX(interp_4tap_vert_sp_16x8_avx512); + p.chroma[X265_CSP_I444].pu[LUMA_16x12].filter_vsp = PFX(interp_4tap_vert_sp_16x12_avx512); + p.chroma[X265_CSP_I444].pu[LUMA_16x16].filter_vsp = PFX(interp_4tap_vert_sp_16x16_avx512); + p.chroma[X265_CSP_I444].pu[LUMA_16x32].filter_vsp = PFX(interp_4tap_vert_sp_16x32_avx512); + p.chroma[X265_CSP_I444].pu[LUMA_16x64].filter_vsp = PFX(interp_4tap_vert_sp_16x64_avx512); + p.chroma[X265_CSP_I444].pu[LUMA_8x8].filter_vpp = PFX(interp_4tap_vert_pp_8x8_avx512); p.chroma[X265_CSP_I444].pu[LUMA_8x16].filter_vpp = PFX(interp_4tap_vert_pp_8x16_avx512); p.chroma[X265_CSP_I444].pu[LUMA_8x32].filter_vpp = PFX(interp_4tap_vert_pp_8x32_avx512); @@ -2712,6 +2726,7 @@ p.chroma[X265_CSP_I422].pu[CHROMA_422_32x32].filter_vsp = PFX(interp_4tap_vert_sp_32x32_avx512); p.chroma[X265_CSP_I422].pu[CHROMA_422_32x48].filter_vsp = PFX(interp_4tap_vert_sp_32x48_avx512); p.chroma[X265_CSP_I422].pu[CHROMA_422_32x64].filter_vsp = PFX(interp_4tap_vert_sp_32x64_avx512); + p.chroma[X265_CSP_I422].pu[CHROMA_422_16x8].filter_vpp = PFX(interp_4tap_vert_pp_16x8_avx512); p.chroma[X265_CSP_I422].pu[CHROMA_422_16x16].filter_vpp = PFX(interp_4tap_vert_pp_16x16_avx512); p.chroma[X265_CSP_I422].pu[CHROMA_422_16x24].filter_vpp = PFX(interp_4tap_vert_pp_16x24_avx512); @@ -2722,6 +2737,17 @@ p.chroma[X265_CSP_I422].pu[CHROMA_422_16x24].filter_vps = PFX(interp_4tap_vert_ps_16x24_avx512); p.chroma[X265_CSP_I422].pu[CHROMA_422_16x32].filter_vps = PFX(interp_4tap_vert_ps_16x32_avx512); p.chroma[X265_CSP_I422].pu[CHROMA_422_16x64].filter_vps = PFX(interp_4tap_vert_ps_16x64_avx512); + p.chroma[X265_CSP_I422].pu[CHROMA_422_16x8].filter_vss = PFX(interp_4tap_vert_ss_16x8_avx512); + p.chroma[X265_CSP_I422].pu[CHROMA_422_16x16].filter_vss = PFX(interp_4tap_vert_ss_16x16_avx512); + p.chroma[X265_CSP_I422].pu[CHROMA_422_16x24].filter_vss = PFX(interp_4tap_vert_ss_16x24_avx512); + p.chroma[X265_CSP_I422].pu[CHROMA_422_16x32].filter_vss = PFX(interp_4tap_vert_ss_16x32_avx512); + p.chroma[X265_CSP_I422].pu[CHROMA_422_16x64].filter_vss = PFX(interp_4tap_vert_ss_16x64_avx512); + p.chroma[X265_CSP_I422].pu[CHROMA_422_16x8].filter_vsp = PFX(interp_4tap_vert_sp_16x8_avx512); + p.chroma[X265_CSP_I422].pu[CHROMA_422_16x16].filter_vsp = PFX(interp_4tap_vert_sp_16x16_avx512); + p.chroma[X265_CSP_I422].pu[CHROMA_422_16x24].filter_vsp = PFX(interp_4tap_vert_sp_16x24_avx512); + p.chroma[X265_CSP_I422].pu[CHROMA_422_16x32].filter_vsp = PFX(interp_4tap_vert_sp_16x32_avx512); + p.chroma[X265_CSP_I422].pu[CHROMA_422_16x64].filter_vsp = PFX(interp_4tap_vert_sp_16x64_avx512); + p.chroma[X265_CSP_I422].pu[CHROMA_422_8x8].filter_vpp = PFX(interp_4tap_vert_pp_8x8_avx512); p.chroma[X265_CSP_I422].pu[CHROMA_422_8x16].filter_vpp = PFX(interp_4tap_vert_pp_8x16_avx512); p.chroma[X265_CSP_I422].pu[CHROMA_422_8x32].filter_vpp = PFX(interp_4tap_vert_pp_8x32_avx512); @@ -2747,6 +2773,7 @@ p.chroma[X265_CSP_I420].pu[CHROMA_420_32x16].filter_vsp = PFX(interp_4tap_vert_sp_32x16_avx512); p.chroma[X265_CSP_I420].pu[CHROMA_420_32x24].filter_vsp = PFX(interp_4tap_vert_sp_32x24_avx512); p.chroma[X265_CSP_I420].pu[CHROMA_420_32x32].filter_vsp = PFX(interp_4tap_vert_sp_32x32_avx512); + p.chroma[X265_CSP_I420].pu[CHROMA_420_16x4].filter_vpp = PFX(interp_4tap_vert_pp_16x4_avx512); p.chroma[X265_CSP_I420].pu[CHROMA_420_16x8].filter_vpp = PFX(interp_4tap_vert_pp_16x8_avx512); p.chroma[X265_CSP_I420].pu[CHROMA_420_16x12].filter_vpp = PFX(interp_4tap_vert_pp_16x12_avx512); @@ -2757,6 +2784,17 @@ p.chroma[X265_CSP_I420].pu[CHROMA_420_16x12].filter_vps = PFX(interp_4tap_vert_ps_16x12_avx512); p.chroma[X265_CSP_I420].pu[CHROMA_420_16x16].filter_vps = PFX(interp_4tap_vert_ps_16x16_avx512); p.chroma[X265_CSP_I420].pu[CHROMA_420_16x32].filter_vps = PFX(interp_4tap_vert_ps_16x32_avx512); + p.chroma[X265_CSP_I420].pu[CHROMA_420_16x4].filter_vss = PFX(interp_4tap_vert_ss_16x4_avx512); + p.chroma[X265_CSP_I420].pu[CHROMA_420_16x8].filter_vss = PFX(interp_4tap_vert_ss_16x8_avx512); + p.chroma[X265_CSP_I420].pu[CHROMA_420_16x12].filter_vss = PFX(interp_4tap_vert_ss_16x12_avx512); + p.chroma[X265_CSP_I420].pu[CHROMA_420_16x16].filter_vss = PFX(interp_4tap_vert_ss_16x16_avx512); + p.chroma[X265_CSP_I420].pu[CHROMA_420_16x32].filter_vss = PFX(interp_4tap_vert_ss_16x32_avx512); + p.chroma[X265_CSP_I420].pu[CHROMA_420_16x4].filter_vsp = PFX(interp_4tap_vert_sp_16x4_avx512); + p.chroma[X265_CSP_I420].pu[CHROMA_420_16x8].filter_vsp = PFX(interp_4tap_vert_sp_16x8_avx512); + p.chroma[X265_CSP_I420].pu[CHROMA_420_16x12].filter_vsp = PFX(interp_4tap_vert_sp_16x12_avx512); + p.chroma[X265_CSP_I420].pu[CHROMA_420_16x16].filter_vsp = PFX(interp_4tap_vert_sp_16x16_avx512); + p.chroma[X265_CSP_I420].pu[CHROMA_420_16x32].filter_vsp = PFX(interp_4tap_vert_sp_16x32_avx512); + p.chroma[X265_CSP_I420].pu[CHROMA_420_8x8].filter_vpp = PFX(interp_4tap_vert_pp_8x8_avx512); p.chroma[X265_CSP_I420].pu[CHROMA_420_8x16].filter_vpp = PFX(interp_4tap_vert_pp_8x16_avx512); p.chroma[X265_CSP_I420].pu[CHROMA_420_8x32].filter_vpp = PFX(interp_4tap_vert_pp_8x32_avx512); diff -r 487307659c36 -r 06da2926583d source/common/x86/ipfilter16.asm --- a/source/common/x86/ipfilter16.asm Tue Nov 14 19:16:49 2017 +0530 +++ b/source/common/x86/ipfilter16.asm Wed Nov 15 14:14:04 2017 +0530 @@ -8272,6 +8272,147 @@ FILTER_VER_PS_CHROMA_64xN_AVX512 64 %endif +%macro PROCESS_CHROMA_VERT_S_16x4_AVX512 1 + movu ym1, [r0] + lea r6, [r0 + 2 * r1] + vinserti32x8 m1, [r6], 1 + movu ym3, [r0 + r1] + vinserti32x8 m3, [r6 + r1], 1 + punpcklwd m0, m1, m3 + pmaddwd m0, m8 + punpckhwd m1, m3 + pmaddwd m1, m8 + + movu ym4, [r0 + 2 * r1] + vinserti32x8 m4, [r6 + 2 * r1], 1 + punpcklwd m2, m3, m4 + pmaddwd m2, m8 + punpckhwd m3, m4 + pmaddwd m3, m8 + + movu ym5, [r0 + r8] + vinserti32x8 m5, [r6 + r8], 1 + punpcklwd m6, m4, m5 + pmaddwd m6, m9 + paddd m0, m6 + punpckhwd m4, m5 + pmaddwd m4, m9 + paddd m1, m4 + + movu ym4, [r0 + 4 * r1] + vinserti32x8 m4, [r6 + 4 * r1], 1 + punpcklwd m6, m5, m4 + pmaddwd m6, m9 + paddd m2, m6 + punpckhwd m5, m4 + pmaddwd m5, m9 + paddd m3, m5 + +%ifidn %1,sp + paddd m0, m7 + paddd m1, m7 + paddd m2, m7 + paddd m3, m7 + + psrad m0, INTERP_SHIFT_SP + psrad m1, INTERP_SHIFT_SP + psrad m2, INTERP_SHIFT_SP + psrad m3, INTERP_SHIFT_SP +%else + psrad m0, 6 + psrad m1, 6 + psrad m2, 6 + psrad m3, 6 +%endif + + packssdw m0, m1 + packssdw m2, m3 + movu [r2], ym0 + movu [r2 + r3], ym2 + vextracti32x8 [r2 + 2 * r3], m0, 1 + vextracti32x8 [r2 + r7], m2, 1 +%endmacro + +;----------------------------------------------------------------------------------------------------------------- +; void interp_4tap_vert(int16_t *src, intptr_t srcStride, int16_t *dst, intptr_t dstStride, int coeffIdx) +;----------------------------------------------------------------------------------------------------------------- +%macro CHROMA_VERT_S_16x4_AVX512 1 +%if ARCH_X86_64 +INIT_ZMM avx512 +cglobal interp_4tap_vert_%1_16x4, 5, 9, 10 + add r1d, r1d + add r3d, r3d + sub r0, r1 + shl r4d, 7 + +%ifdef PIC + lea r5, [tab_ChromaCoeffV_avx512] + lea r5, [r5 + r4] +%else + lea r5, [tab_ChromaCoeffV_avx512 + r4] +%endif + + mova m8, [r5] + mova m9, [r5 + mmsize] +%ifidn %1, sp + vbroadcasti32x4 m7, [INTERP_OFFSET_SP] +%endif + lea r7, [3 * r3] + lea r8, [3 * r1] + PROCESS_CHROMA_VERT_S_16x4_AVX512 %1 + RET +%endif +%endmacro + +CHROMA_VERT_S_16x4_AVX512 ss +CHROMA_VERT_S_16x4_AVX512 sp + +%macro FILTER_VER_S_CHROMA_16xN_AVX512 2 +INIT_ZMM avx512 +cglobal interp_4tap_vert_%1_16x%2, 5, 9, 10 + add r1d, r1d + add r3d, r3d + sub r0, r1 + shl r4d, 7 + +%ifdef PIC + lea r5, [tab_ChromaCoeffV_avx512] + lea r5, [r5 + r4] +%else + lea r5, [tab_ChromaCoeffV_avx512 + r4] +%endif + + mova m8, [r5] + mova m9, [r5 + mmsize] +%ifidn %1, sp + vbroadcasti32x4 m7, [INTERP_OFFSET_SP] +%endif + lea r7, [3 * r3] + lea r8, [3 * r1] +%rep %2/4 - 1 + PROCESS_CHROMA_VERT_S_16x4_AVX512 %1 + lea r0, [r0 + 4 * r1] + lea r2, [r2 + 4 * r3] +%endrep + PROCESS_CHROMA_VERT_S_16x4_AVX512 %1 + RET +%endmacro + +%if ARCH_X86_64 + FILTER_VER_S_CHROMA_16xN_AVX512 ss, 8 + FILTER_VER_S_CHROMA_16xN_AVX512 ss, 12 + FILTER_VER_S_CHROMA_16xN_AVX512 ss, 16 + FILTER_VER_S_CHROMA_16xN_AVX512 ss, 24 + FILTER_VER_S_CHROMA_16xN_AVX512 ss, 32 + FILTER_VER_S_CHROMA_16xN_AVX512 ss, 64 + FILTER_VER_S_CHROMA_16xN_AVX512 sp, 8 + FILTER_VER_S_CHROMA_16xN_AVX512 sp, 12 + FILTER_VER_S_CHROMA_16xN_AVX512 sp, 16 + FILTER_VER_S_CHROMA_16xN_AVX512 sp, 24 + FILTER_VER_S_CHROMA_16xN_AVX512 sp, 32 + FILTER_VER_S_CHROMA_16xN_AVX512 sp, 64 +%endif + %macro PROCESS_CHROMA_VERT_S_24x8_AVX512 1 movu ym1, [r0] lea r6, [r0 + 2 * r1] _______________________________________________ x265-devel mailing list x265-devel@videolan.org https://mailman.videolan.org/listinfo/x265-devel