>>> On 16.12.14 at 09:55, <chao.p.p...@linux.intel.com> wrote: > Any comments from you? It would be greatly appreciated if you can look > at this when you have time. Your comments are always important to me :)
I don't think I have to say much here: > On Fri, Dec 12, 2014 at 08:27:57PM +0800, Chao Peng wrote: >> Implementation Description >> ========================== >> In this design, one principal is that only implementing the cache >> enforcement mechanism in hypervisor but leaving the cache allocation >> policy to user space tool stack. In this way some complex governors then >> can be implemented in tool stack. With this, the changes to the hypervisor ought to be quite limited, even if length of the list you give seems long at a first glance, and hence I'm fine with the concept. >> Hardware Limitation & Performance Improvement >> ============================================= >> As the COS of PCPU in IA32_PQR_ASSOC is changed on each VCPU context >> switch. If the change is frequent then hardware may fail to strictly >> enforce the cache allocation basing on the specified COS. This certainly would deserve a little more explanation: What's the value of the functionality if one can't rely on it being enforced by hardware at all times? Jan _______________________________________________ Xen-devel mailing list Xen-devel@lists.xen.org http://lists.xen.org/xen-devel