Hi Jan,
On 05/05/17 11:16, Jan Beulich wrote:
On 04.05.17 at 23:30, <mohit.gamb...@oracle.com> wrote:
Setting Pin Control (PC) bit (19) in MSR_P6_EVNTSEL results in a General
Protection Fault and thus results in a hypervisor crash. This behavior has
been observed on two generations of Intel processors namely, Haswell and
Broadwell. Other Intel processor generations were not tested. However, it
does seem to be a possible erratum that hasn't yet been confirmed by Intel.
To fix the problem this patch masks PC bit and returns an error in
case any guest tries to write to it on any Intel processor. In addition
to the fact that setting this bit crashes the hypervisor on Haswell and
Broadwell, the PC flag bit toggles a hardware pin on the physical CPU
every time the programmed event occurs and the hardware behavior in
response to the toggle is undefined in the SDM, which makes this bit
unsafe to be used by guests and hence should be masked on all machines.
Signed-off-by: Mohit Gambhir <mohit.gamb...@oracle.com>
Reviewed-by: Jan Beulich <jbeul...@suse.com>
Iirc the intention was to have this in 4.9, in which case you should
have Cc-ed Juline (now added).
Release-acked-by: Julien Grall <julien.gr...@arm.com>
Cheers,
--
Julien Grall
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