flight 113125 xen-unstable-smoke real [real]
http://logs.test-lab.xenproject.org/osstest/logs/113125/
Failures and problems with tests :-(
Tests which did not succeed and are blocking,
including tests which could not be run:
build-arm64 <job status> broken
test-arm64-arm64-xl-xsm <job status> broken
build-arm64-pvops <job status> broken
Tests which did not succeed, but are not blocking:
test-arm64-arm64-xl-xsm 1 build-check(1) blocked n/a
build-arm64-pvops 2 hosts-allocate broken like 113039
build-arm64-pvops 3 capture-logs broken like 113039
build-arm64 2 hosts-allocate broken like 113039
build-arm64 3 capture-logs broken like 113039
test-armhf-armhf-xl 13 migrate-support-check fail never pass
test-armhf-armhf-xl 14 saverestore-support-check fail never pass
test-amd64-amd64-libvirt 13 migrate-support-check fail never pass
version targeted for testing:
xen 65c256266477e72f455a45a54597d5816646c74f
baseline version:
xen 6dfb43d6f2cd8ea6274d203ca00ecfc7c565f11a
Last test of basis 113039 2017-09-04 15:02:08 Z 2 days
Failing since 113052 2017-09-05 13:01:29 Z 1 days 21 attempts
Testing same since 113097 2017-09-06 17:02:46 Z 0 days 9 attempts
------------------------------------------------------------
People who touched revisions under test:
Alexandru Isaila <aisa...@bitdefender.com>
Andrew Cooper <andrew.coop...@citrix.com>
Jan Beulich <jbeul...@suse.com>
Olaf Hering <o...@aepfle.de>
Tamas K Lengyel <ta...@tklengyel.com>
Wei Liu <wei.l...@citrix.com>
Yi Sun <yi.y....@linux.intel.com>
jobs:
build-amd64 pass
build-arm64 broken
build-armhf pass
build-amd64-libvirt pass
build-arm64-pvops broken
test-armhf-armhf-xl pass
test-arm64-arm64-xl-xsm broken
test-amd64-amd64-xl-qemuu-debianhvm-i386 pass
test-amd64-amd64-libvirt pass
------------------------------------------------------------
sg-report-flight on osstest.test-lab.xenproject.org
logs: /home/logs/logs
images: /home/logs/images
Logs, config files, etc. are available at
http://logs.test-lab.xenproject.org/osstest/logs
Explanation of these reports, and of osstest in general, is at
http://xenbits.xen.org/gitweb/?p=osstest.git;a=blob;f=README.email;hb=master
http://xenbits.xen.org/gitweb/?p=osstest.git;a=blob;f=README;hb=master
Test harness code can be found at
http://xenbits.xen.org/gitweb?p=osstest.git;a=summary
broken-job build-arm64 broken
broken-job test-arm64-arm64-xl-xsm broken
broken-job build-arm64-pvops broken
broken-step build-arm64-pvops hosts-allocate
broken-step build-arm64-pvops capture-logs
broken-step build-arm64 hosts-allocate
broken-step build-arm64 capture-logs
Not pushing.
------------------------------------------------------------
commit 65c256266477e72f455a45a54597d5816646c74f
Author: Yi Sun <yi.y....@linux.intel.com>
Date: Mon Sep 4 19:01:44 2017 +0800
tools: change the type of '*nr' in 'libxl_psr_cat_get_info'
Due to historical reason, type of parameter '*nr' in
'libxl_psr_cat_get_info'
is 'int'. But this is not right. It should be 'unsigned int'. This patch
fixes
this and does related changes.
Suggested-by: Roger Pau Monné <roger....@citrix.com>
Signed-off-by: Yi Sun <yi.y....@linux.intel.com>
Acked-by: Wei Liu <wei.l...@citrix.com>
commit 5fe3e6a74afa21dd4f4abc18b47ed0f2e1550329
Author: Yi Sun <yi.y....@linux.intel.com>
Date: Mon Sep 4 19:01:43 2017 +0800
tools: use '__i386__' and '__x86_64__' to replace PSR macros
The libxl interfaces and related functions are not necessary to be included
by
'LIBXL_HAVE_PSR_CMT' and 'LIBXL_HAVE_PSR_CAT'. So replace them to common x86
macros. Furthermore, only compile 'xl_psr.c' under x86.
Suggested-by: Roger Pau Monné <roger....@citrix.com>
Suggested-by: Wei Liu <wei.l...@citrix.com>
Signed-off-by: Yi Sun <yi.y....@linux.intel.com>
Reviewed-by: Roger Pau Monné <roger....@citrix.com>
Acked-by: Wei Liu <wei.l...@citrix.com>
commit 0829a6bdbdc6b79990bd0668e847275b6a2717e5
Author: Jan Beulich <jbeul...@suse.com>
Date: Wed Sep 6 12:32:00 2017 +0200
x86: introduce and use setup_force_cpu_cap()
For XEN_SMEP and XEN_SMAP to not be cleared while bringing up APs we'd
need to clone the respective hack used for CPUID_FAULTING. Introduce an
inverse of setup_clear_cpu_cap() instead, but let clearing of features
overrule forced setting of them.
XEN_SMAP being wrong post-boot is a problem specifically for live
patching, as a live patch may need alternative instruction patching
keyed off of that feature flag.
Reported-by: Sarah Newman <secur...@prgmr.com>
Signed-off-by: Jan Beulich <jbeul...@suse.com>
Reviewed-by: Andrew Cooper <andrew.coop...@citrix.com>
commit fd903a35daf3e7e6bfa782b18dfd43746f940bed
Author: Andrew Cooper <andrew.coop...@citrix.com>
Date: Tue Sep 5 17:54:45 2017 +0100
x86/traps: Fix show_page_walk() to avoid printing trailing whitespace
This moves the L2 line to be consistent with the L3 line.
Signed-off-by: Andrew Cooper <andrew.coop...@citrix.com>
Reviewed-by: Wei Liu <wei.l...@citrix.com>
Acked-by: Jan Beulich <jbeul...@suse.com>
commit 12257de3cfff9b4ffa0b7379ef82c9ad7c8dbec9
Author: Andrew Cooper <andrew.coop...@citrix.com>
Date: Fri Sep 1 17:05:21 2017 +0000
xen: Drop asmlinkage everywhere
asmlinkage is defined as nothing on all architectures, and not used
consistently anywhere, even in common code. Remove it all.
Signed-off-by: Andrew Cooper <andrew.coop...@citrix.com>
Acked-by: Jan Beulich <jbeul...@suse.com>
Reviewed-by: Stefano Stabellini <sstabell...@kernel.org>
commit 150dd3946c521a9257c4dd97e6190c6b0df680d3
Author: Olaf Hering <o...@aepfle.de>
Date: Tue Sep 5 11:03:38 2017 +0200
libxc/bitops: correct comment for bitmap_size
The returned value represents now units of bytes instead of longs.
Fixes commit 11d0044a16 ("tools/libxc: Modify bitmap operations to
take void pointers").
Signed-off-by: Olaf Hering <o...@aepfle.de>
Acked-by: Wei Liu <wei.l...@citrix.com>
commit 15e4dd5e866b43bbc2d438034445c6582db1d3de
Author: Alexandru Isaila <aisa...@bitdefender.com>
Date: Wed Aug 30 12:04:00 2017 +0300
common/vm_event: Initialize vm_event lists on domain creation
The patch splits the vm_event into three structures:vm_event_share,
vm_event_paging, vm_event_monitor. The allocation for the
structure is moved to vm_event_enable so that it can be
allocated/init when needed and freed in vm_event_disable.
Signed-off-by: Alexandru Isaila <aisa...@bitdefender.com>
Acked-by: Jan Beulich <jbeul...@suse.com>
Acked-by: Wei Liu <wei.l...@citrix.com>
Acked-by: Tamas K Lengyel <ta...@tklengyel.com>
commit eb4e638a474792137414f03409e78477810c3436
Author: Jan Beulich <jbeul...@suse.com>
Date: Tue Sep 5 17:32:43 2017 +0200
x86emul: correct EVEX decoding
While these are latent issues only for now, correct them right away:
- unnamed (in the SDM) EVEX bits need to be set/clear respectively
- EVEX.V' (called RX in our code) needs to uniformly be 1 in non-64-bit
modes,
- EXEX.R' (called R in our code) is uniformly being ignored in
non-64-bit modes.
Signed-off-by: Jan Beulich <jbeul...@suse.com>
Reviewed-by: Andrew Cooper <andrew.coop...@citrix.com>
commit a6488965ca3ec30f2e0b7022b539bba78c2aeede
Author: Jan Beulich <jbeul...@suse.com>
Date: Tue Sep 5 17:32:05 2017 +0200
x86emul: correct VEX.L handling for VCVT{,T}S{S,D}2SI
Recent changes to the SDM (and XED) have made clear that older hardware
raising #UD when the bit is set was really an erratum. Generalize the
so far AMD-only override.
Signed-off-by: Jan Beulich <jbeul...@suse.com>
Reviewed-by: Andrew Cooper <andrew.coop...@citrix.com>
commit 9c2babd05a213f8802e3cc1c64a2af932b5cbd7d
Author: Jan Beulich <jbeul...@suse.com>
Date: Tue Sep 5 17:31:01 2017 +0200
x86emul: correct VEX.W handling for non-64-bit VPINSRD
Going though the XED commits from the last couple of months made me
notice that VPINSRD, other than VPEXTRD, does not clear VEX.W for non-
64-bit modes, leading to an insertion of stray 32-bits of zero in case
the original instruction had the bit set.
Also remove a pointless fall-through in VPEXTRW handling, bringing
things in line with VPINSRW.
Signed-off-by: Jan Beulich <jbeul...@suse.com>
Reviewed-by: Andrew Cooper <andrew.coop...@citrix.com>
commit 4d3f0fde471e7588ce512eaff1abdab209d8cd4b
Author: Andrew Cooper <andrew.coop...@citrix.com>
Date: Tue Sep 5 09:40:58 2017 +0100
x86/emul: Fix the handling of unimplemented Grp7 instructions
Grp7 is abnormally complicated to decode, even by x86's standards, with
{s,l}msw being the problematic cases.
Previously, any value which fell through the first switch statement (looking
for instructions with entirely implicit operands) would be interpreted by
the
second switch statement (handling instructions with memory operands).
Unimplemented instructions would then hit the #UD case for having a
non-memory
operand, rather than taking the cannot_emulate path.
Consolidate the two switch statements into a single one, using ranges to
cover
the instructions with memory operands.
Reported-by: Petre Pircalabu <ppircal...@bitdefender.com>
Signed-off-by: Andrew Cooper <andrew.coop...@citrix.com>
Reviewed-by: Jan Beulich <jbeul...@suse.com>
(qemu changes not included)
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