On 28/09/17 23:49, Andre Przywara wrote:
Hi,
Hi,
On 09/28/2017 01:03 PM, Julien Grall wrote:
#define SUNXI_WDT_MODE 0x04
-#define SUNXI_WDT_MODEADDR (SUNXI_WDT_BASE + SUNXI_WDT_MODE)
#define SUNXI_WDT_MODE_EN (1 << 0)
#define SUNXI_WDT_MODE_RST_EN (1 << 1)
-static void sunxi_reset(void)
+static void sunxi_reset(u32 base)
{
void __iomem *wdt;
- wdt = ioremap_nocache(SUNXI_WDT_MODEADDR & PAGE_MASK, PAGE_SIZE);
+ wdt = ioremap_nocache((base + SUNXI_WDT_MODE) & PAGE_MASK,
PAGE_SIZE);
if ( !wdt )
{
dprintk(XENLOG_ERR, "Unable to map watchdog register!\n");
@@ -42,19 +42,35 @@ static void sunxi_reset(void)
/* Enable watchdog to trigger a reset after 500 ms: */
writel(SUNXI_WDT_MODE_EN | SUNXI_WDT_MODE_RST_EN,
- wdt + (SUNXI_WDT_MODEADDR & ~PAGE_MASK));
+ wdt + ((base + SUNXI_WDT_MODE) & ~PAGE_MASK));
iounmap(wdt); >
for (;;)
wfi();
}
-static const char * const sunxi_dt_compat[] __initconst =
+static void sunxi_a20_reset(void)
+{
+ sunxi_reset(SUNXI_WDT_A20_BASE);
+}
+
+static void sunxi_h5_reset(void)
+{
+ sunxi_reset(SUNXI_WDT_H5_BASE);
If I read correctly the Device-Tree for
(linux/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi), the firmware is
supporting PSCI 0.2.
PSCI 0.2 provides call for power-off/reset, so implementation the
reset callback should not be necessary.
Yes, indeed, on the H5 PSCI 0.2 reset works via ATF.
Similarly the cubietrucks we have in osstest are using PSCI 0.2 and
should not need the reset. Andre do you know if it is the case for all
the A20?
It claims 0.2, but in fact it seems not to be fully compliant, as (from
looking at the code) U-Boot lacks the reset and poweroff calls. But it
looks rather straight-forward to add them, as U-Boot knows how to reset
and one would just need to wire up psci_system_reset to this.
Hmmm ok :/. Please ignore my suggestion below to drop reset callback for
all the allwinner platforms.
Cheers,
--
Julien Grall
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