Gather the affected handlers in a single place per trap type.
Signed-off-by: Ian Campbell <ian.campb...@citrix.com>
---
xen/arch/arm/traps.c | 71 ++++++++++++++++++++++++++++++++++++++++++--------
1 file changed, 60 insertions(+), 11 deletions(-)
diff --git a/xen/arch/arm/traps.c b/xen/arch/arm/traps.c
index 518f047..0ab5e56 100644
--- a/xen/arch/arm/traps.c
+++ b/xen/arch/arm/traps.c
@@ -1816,6 +1816,28 @@ static void do_cp14_32(struct cpu_user_regs *regs, const
union hsr hsr)
case HSR_CPREG32(DBGOSDLR):
return handle_raz_wi(regs, r, cp32.read, hsr, 1);
+ /*
+ * MDCR_EL2.TDA
+ *
+ * ARMv7 (DDI 0406C.b): B1.14.15
+ * ARMv8 (DDI 0487A.d): D1-1510 Table D1-59
+ *
+ * Unhandled:
+ * DBGDCCINT
+ * DBGDTRRXint
+ * DBGDTRTXint
+ * DBGWFAR
+ * DBGDTRTXext
+ * DBGDTRRXext,
+ * DBGBXVR<n>
+ * DBGCLAIMSET
+ * DBGCLAIMCLR
+ * DBGAUTHSTATUS
+ * DBGDEVID
+ * DBGDEVID1
+ * DBGDEVID2
+ * DBGOSECCR
+ */
case HSR_CPREG32(DBGDIDR):
/*
* Read-only register. Accessible by EL0 if DBGDSCRext.UDCCdis
@@ -1925,6 +1947,17 @@ static void do_cp14_dbg(struct cpu_user_regs *regs,
const union hsr hsr)
return;
}
+ /*
+ * MDCR_EL2.TDOSA
+ *
+ * ARMv7 (DDI 0406C.b): B1.14.15
+ * ARMv8 (DDI 0487A.d): D1-1509 Table D1-58
+ *
+ * Unhandled:
+ * DBGDTRTXint
+ * DBGDTRRXint
+ */
+
gdprintk(XENLOG_ERR,
"%s p14, %d, r%d, r%d, cr%d @ 0x%"PRIregister"\n",
cp64.read ? "mrrc" : "mcrr",
@@ -1993,15 +2026,38 @@ static void do_sysreg(struct cpu_user_regs *regs,
case HSR_SYSREG_OSDLR_EL1:
return handle_raz_wi(regs, x, hsr.sysreg.read, hsr, 1);
- /* RAZ/WI registers: */
- /* - Debug */
+ /*
+ * MDCR_EL2.TDA
+ *
+ * ARMv8 (DDI 0487A.d): D1-1510 Table D1-59
+ *
+ * Unhandled:
+ * MDCCINT_EL1
+ * DBGDTR_EL0
+ * DBGDTRRX_EL0
+ * DBGDTRTX_EL0
+ * OSDTRRX_EL1
+ * OSDTRTX_EL1
+ * OSECCR_EL1
+ * DBGCLAIMSET_EL1
+ * DBGCLAIMCLR_EL1
+ * DBGAUTHSTATUS_EL1
+ */
case HSR_SYSREG_MDSCR_EL1:
- /* - Breakpoints */
+ return handle_raz_wi(regs, x, hsr.sysreg.read, hsr, 1);
+ case HSR_SYSREG_MDCCSR_EL0:
+ /*
+ * Accessible at EL0 only if MDSCR_EL1.TDCC is set to 0. We emulate
that
+ * register as RAZ/WI above. So RO at both EL0 and EL1.
+ */
+ return handle_ro_raz(regs, x, hsr.sysreg.read, hsr, 0);
HSR_SYSREG_DBG_CASES(DBGBVR):
HSR_SYSREG_DBG_CASES(DBGBCR):
- /* - Watchpoints */
HSR_SYSREG_DBG_CASES(DBGWVR):
HSR_SYSREG_DBG_CASES(DBGWCR):
+ return handle_raz_wi(regs, x, hsr.sysreg.read, hsr, 1);
+
+ /* RAZ/WI registers: */
/* - Perf monitors */
case HSR_SYSREG_PMINTENSET_EL1:
case HSR_SYSREG_PMINTENCLR_EL1:
@@ -2011,13 +2067,6 @@ static void do_sysreg(struct cpu_user_regs *regs,
*/
return handle_raz_wi(regs, x, hsr.sysreg.read, hsr, 1);
- case HSR_SYSREG_MDCCSR_EL0:
- /*
- * Accessible at EL0 only if MDSCR_EL1.TDCC is set to 0. We emulate
that
- * register as RAZ/WI above. So RO at both EL0 and EL1.
- */
- return handle_ro_raz(regs, x, hsr.sysreg.read, hsr, 0);
-
/* - Perf monitors */
case HSR_SYSREG_PMUSERENR_EL0:
/* RO at EL0. RAZ/WI at EL1 */
--
1.7.10.4
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