Hi Ian,
On 31/03/2015 12:07, Ian Campbell wrote:
Reference the bit which enables the trap and the section/page which
describes what that bit enables.
These ones are pretty trivial, included for completeness.
Signed-off-by: Ian Campbell <ian.campb...@citrix.com>
---
xen/arch/arm/traps.c | 17 +++++++++++++++++
1 file changed, 17 insertions(+)
diff --git a/xen/arch/arm/traps.c b/xen/arch/arm/traps.c
index c9c98d3..70e1b4d 100644
--- a/xen/arch/arm/traps.c
+++ b/xen/arch/arm/traps.c
@@ -2083,6 +2083,12 @@ asmlinkage void do_trap_hypervisor(struct cpu_user_regs
*regs)
switch (hsr.ec) {
case HSR_EC_WFI_WFE:
+ /*
+ * HSR_EL2.TWI, HSR_EL2.TWE
Typo: I should be HCR not HSR.
+ *
+ * ARMv7 (DDI 0406C.b): B1.14.9
+ * ARMv8 (DDI 0487A.d): D1-1505 Table D1-51
It's a bit confusing that you are using section for ARMv7 and page for
ARMv8.
+ */
if ( !check_conditional_instr(regs, hsr) )
{
advance_pc(regs, hsr);
@@ -2125,6 +2131,12 @@ asmlinkage void do_trap_hypervisor(struct cpu_user_regs
*regs)
do_cp(regs, hsr);
break;
case HSR_EC_SMC32:
+ /*
+ * HSR_EL2.TSC
HCR
+ *
+ * ARMv7 (DDI 0406C.b): B1.14.8
+ * ARMv8 (DDI 0487A.d): D1-1501 Table D1-44
+ */
GUEST_BUG_ON(!psr_mode_is_32bit(regs->cpsr));
perfc_incr(trap_smc32);
inject_undef32_exception(regs);
@@ -2153,6 +2165,11 @@ asmlinkage void do_trap_hypervisor(struct cpu_user_regs
*regs)
do_trap_hypercall(regs, ®s->x16, hsr.iss);
break;
case HSR_EC_SMC64:
+ /*
+ * HSR_EL2.TSC
HCR
+ *
+ * ARMv8 (DDI 0487A.d): D1-1501 Table D1-44
+ */
GUEST_BUG_ON(psr_mode_is_32bit(regs->cpsr));
perfc_incr(trap_smc64);
inject_undef64_exception(regs, hsr.len);
Regards,
--
Julien Grall
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