This traps variety of implementation defined registers, so add a note
to the default case of the respective handler.
Signed-off-by: Ian Campbell <ian.campb...@citrix.com>
Reviewed-by: Julien Grall <julien.gr...@citrix.com>
---
v2: Typo in subject
---
xen/arch/arm/traps.c | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
diff --git a/xen/arch/arm/traps.c b/xen/arch/arm/traps.c
index 522701b..d908738 100644
--- a/xen/arch/arm/traps.c
+++ b/xen/arch/arm/traps.c
@@ -1704,6 +1704,14 @@ static void do_cp15_32(struct cpu_user_regs *regs,
*/
return handle_raz_wi(regs, r, cp32.read, hsr, 1);
+ /*
+ * HCR_EL2.TIDCP
+ *
+ * ARMv7 (DDI 0406C.b): B1.14.3
+ * ARMv8 (DDI 0487A.d): D1-1501 Table D1-43
+ *
+ * And all other unknown registers.
+ */
default:
gdprintk(XENLOG_ERR,
"%s p15, %d, r%d, cr%d, cr%d, %d @ 0x%"PRIregister"\n",
@@ -1954,6 +1962,14 @@ static void do_sysreg(struct cpu_user_regs *regs,
dprintk(XENLOG_WARNING,
"Emulation of sysreg ICC_SGI0R_EL1/ASGI1R_EL1 not
supported\n");
return inject_undef64_exception(regs, hsr.len);
+
+ /*
+ * HCR_EL2.TIDCP
+ *
+ * ARMv8 (DDI 0487A.d): D1-1501 Table D1-43
+ *
+ * And all other unknown registers.
+ */
default:
{
const struct hsr_sysreg sysreg = hsr.sysreg;
--
1.7.10.4
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