Hi Ian, On 05/05/15 14:17, Ian Campbell wrote: > On Fri, 2015-05-01 at 11:40 +1000, Edgar E. Iglesias wrote: >> From: "Edgar E. Iglesias" <edgar.igles...@xilinx.com> >> >> Hi, >> >> This is a fix for the issue I'm seeing on ZynqMP with missmatched >> setup of the SMMU and the shared p2m page-tables with the CPU. > > Looking back at previous conversations it seems like your SMMU handles > fewer input bits than the second stage of the regular MMU, is that > right? > > Is there an architectural constraint that bits(SMMU) <= bits(MMU-s2)?
His problem is bits(MMU-s2) <= bits(SMMU). Although, we were talking about hardware where the bits(SMMU) <= bits(MMU-s2). I have Seattle in mind but I haven't yet feedback from Suravee (in CC). Suravee, do you have any input? Having the bits(SMMU) <= bits(MMU-s2) would restrict the P2M to use 40 bits. Anything above won't be accessible to DOM0 because of the 1:1 mapping. Regards, -- Julien Grall _______________________________________________ Xen-devel mailing list Xen-devel@lists.xen.org http://lists.xen.org/xen-devel
