On 05/27/2015 10:26 AM, Jan Beulich wrote:
On 27.05.15 at 15:44, <boris.ostrov...@oracle.com> wrote:
Sorry, I meant amd/intel members of the union below (I forgot we were
already in the arch header file):
+ /*
+ * Vendor-specific PMU registers.
+ * RW for both hypervisor and guest.
+ * Guest's updates to this field are verified and then loaded by the
+ * hypervisor into hardware during XENPMU_flush
+ */
+ union {
+ struct xen_pmu_amd_ctxt amd;
+ struct xen_pmu_intel_ctxt intel;
+
+ /*
+ * Padding for contexts (fixed parts only, does not include MSR banks
+ * that are specified by offsets)
+ */
+#define XENPMU_CTXT_PAD_SZ 128
+ uint8_t pad[XENPMU_CTXT_PAD_SZ];
+ } c;
+};
I think they are first used in patch 11 so I assume you also want me to
just keep the pad here (with a comment explaining why it is here) until
that patch.
Ah, those ones I simply recalled having checked in the previous
version already.
But should they they also not be defined until later patch, to be
consistent with how lapic_lvtpc's definition is deferred?
-boris
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