On Thu, 2015-06-11 at 11:05 +0200, Roger Pau Monné wrote: > El 10/06/15 a les 21.21, Julien Grall ha escrit: > >> If there is a reason for this restriction/trade off then it should be > >> spelled out as part of the design document, as should other such design > >> decisions (which would include explaining where this differs from how > >> things work for x86 why they must differ). > > > > On x86, for HVM the MMIO mapping is done by QEMU. I know that Roger is > > working on PCI passthrough for PVH. PVH is very similar to ARM guest and > > I expect to see a similar needs for MMIO mapping. It would be good if we > > can come up with a common interface. > > I've kind of left that apart in favour of the new boot ABI that we are > currently discussing, but IIRC the plan was to use > XENMEM_add_to_physmap_range by adding a new phys_map_space and the > physical MMIO pages would be specified in the idxs field.
This sounds ok, and preferable to an entirely new hypercall. One question is how to handle writes to the BAR registers in this scenario. If we allow changes (does PCI allow us to not allow them?) then the guest p2m would need updating too... Ian. _______________________________________________ Xen-devel mailing list Xen-devel@lists.xen.org http://lists.xen.org/xen-devel
