>>> On 18.06.15 at 16:55, <[email protected]> wrote:
> I'm John's colleague. We looked into the details of the tracing data, and
> found that the number of MSR_IA32_APICTMICT_MSR
> event is quite high when apic-v is enabled(about 9x more compared with apic-v
> disabled).
>
> Below is the details:
>
> EXIT_REASON_MSR_WRITE
> apicv on:
> MSR= 0x00000838(MSR_IA32_APICTMICT_MSR) count= 111480
> MSR= 0x00000830(x2APIC Interrupt Command Register) count= 350
> Total count = 111830
>
> apicv off:
> MSR= 0x00000838(MSR_IA32_APICTMICT_MSR) count= 13595
> MSR= 0x00000830(x2APIC Interrupt Command Register) count= 254
> MSR= 0x0000080b(MSR_IA32_APICEOI_MSR) count= 215760
> Total count = 229609
Yes, accesses to this MSR get specifically intercepted when using
APICv (see vmx_vlapic_msr_changed()). I'm therefore surprised
that you see more than a handful of writes come through in the
opposite case.
As the processing of the writes themselves isn't very involved, I
wonder whether the higher count really contributes to your
problem in a measurable way. I wonder whether bad effects of
create_periodic_time() being repeatedly called (we observed such
before) might instead play a role here. Iirc you had taken a
trace already - could you extract a meaningful subset of
HVM_EMUL_LAPIC_{START,STOP}_TIMER events from it?
Jan
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