etc along with adjusting the existing gating of PML on AD being
available (perhaps by simply stripping the respective bit from what
we read from MSR_IA32_VMX_EPT_VPID_CAP). Of course this
then ignores the fact that the erratum only affects the A bit, but
I think we can live with that.
I also think the currently slightly strange setting of the ept_ad bit
should be changed: There's no point setting the bit for domains
not getting PML enabled (and incurring the overhead of the
hardware updating the bits); imo this should instead be done in
ept_enable_pml() / vmx_domain_enable_pml() (and undone in
the respective disable function).
Yep.
Just as a note, in the non PML case, the AD enable bit in EPTP is left
clear, which means that the A/D bits in the EPTs have no effect.
Therefore, despite the unconditional setting of the A/D bits, there is
still no MMU overhead.
~Andrew
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