On Tue, 2015-11-10 at 16:20 +0000, Ian Campbell wrote:
> ... instead of artificially masking the timer interrupt in the timer
> state
Julien pointed out IRL that this now causes vgic_{enable,disable}_irqs to
call into the h/w driver for that irq, which is new for a PPI. The GICv3
hook for enable/disable will write to the local redistributor, but a cpu is
entitled to do write to another vcpus GICR, for the banked registers
associated with PPIs. The upshot is that we will enable/disable the local
PPI instead of the remote one as expected.
This will require some thought (or if I'm really lucky some careful reading
of the spec to turn this into the expected behaviour for such banked
registers, doubtful...)...
Ian.
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