Hi Ian, On 16/11/15 13:33, Ian Campbell wrote: > On Fri, 2015-11-13 at 11:54 +0000, Julien Grall wrote: >> The 2 registers are not described in the software spec (ARM IHI 0069A) >> and their offsets are marked "implementation defined". > > They do exist in "PRD03-GENC-010745 24.0", in that they are mentioned as > having corresponding completion bits in GICR_SYNCR in that version, but > seem to never be defined themselves. I suppose they were a remnant of an > older spec. No need to discuss that in the commit message though.
At the end of the GICR_SYNCR section the spec says that this register is only mandatory in implementation which supports LPIs and doesn't include an ITS. For now, we don't support LPIs at all and in the future it will be through the ITS, so they are effectively implementation defined in our use case. >> >> Signed-off-by: Julien Grall <julien.gr...@citrix.com> > > Acked-by: Ian Campbell <ian.campb...@citrix.com> Thank you! Regards, -- Julien Grall _______________________________________________ Xen-devel mailing list Xen-devel@lists.xen.org http://lists.xen.org/xen-devel
