The offset is 0x0D00 and not 0x0F80.
Also re-order the definition to keep all the definitions ordered.
Signed-off-by: Julien Grall <julien.gr...@citrix.com>
Acked-by: Ian Campbell <ian.campb...@citrix.com>
---
Changes in v2:
- Add Ian's acked-by
---
xen/include/asm-arm/gic_v3_defs.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/xen/include/asm-arm/gic_v3_defs.h
b/xen/include/asm-arm/gic_v3_defs.h
index 89a3548..34e8b0a 100644
--- a/xen/include/asm-arm/gic_v3_defs.h
+++ b/xen/include/asm-arm/gic_v3_defs.h
@@ -96,7 +96,6 @@
/* GICR for SGI's & PPI's */
#define GICR_IGROUPR0 (0x0080)
-#define GICR_IGRPMODR0 (0x0F80)
#define GICR_ISENABLER0 (0x0100)
#define GICR_ICENABLER0 (0x0180)
#define GICR_ISPENDR0 (0x0200)
@@ -107,6 +106,7 @@
#define GICR_IPRIORITYR7 (0x041C)
#define GICR_ICFGR0 (0x0C00)
#define GICR_ICFGR1 (0x0C04)
+#define GICR_IGRPMODR0 (0x0D00)
#define GICR_NSACR (0x0E00)
#define GICR_TYPER_PLPIS (1U << 0)
--
2.1.4
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