>>> On 04.01.18 at 01:15, <andrew.coop...@citrix.com> wrote:
> @@ -31,6 +33,38 @@ static inline void init_shadow_spec_ctrl_state(void)
> info->shadow_spec_ctrl = info->use_shadow_spec_ctrl = 0;
> }
>
> +/* WARNING! `ret`, `call *`, `jmp *` not safe after this call. */
> +static always_inline void spec_ctrl_enter_idle(struct cpu_info *info)
> +{
> + uint32_t val = 0;
> +
> + /*
> + * Latch the new shadow value, then enable shadowing, then update the
> MSR.
> + * There are no SMP issues here; only local processor ordering concerns.
> + */
> + info->shadow_spec_ctrl = val;
> + barrier();
> + info->use_shadow_spec_ctrl = true;
> + barrier();
> + asm volatile (ALTERNATIVE(ASM_NOP3, "wrmsr", X86_FEATURE_XEN_IBRS_SET)
> + :: "a" (val), "c" (MSR_SPEC_CTRL), "d" (0) : "memory");
Missing blanks immediately inside the outermost parentheses (also
another time further down).
Jan
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