On Thu, Jan 04, 2018 at 12:15:44AM +0000, Andrew Cooper wrote: > Contemporary processors are gaining Indirect Branch Controls via microcode > updates. Intel are introducing one bit to indicate IBRS and IBPB support, and > a second bit for STIBP. AMD are introducing IPBP only, so enumerate it with a > separate bit. > > Furthermore, depending on compiler and microcode availability, we may want to > run Xen with IBRS set, or clear. > > To use these facilities, we synthesise separate IBRS and IBPB bits for > internal use. A lot of infrastructure is required before these features are > safe to offer to guests. > > Signed-off-by: Andrew Cooper <andrew.coop...@citrix.com> > --- > v4: > * Update for AMD, drop acks/reviews. > --- > tools/libxl/libxl_cpuid.c | 3 +++ > tools/misc/xen-cpuid.c | 12 ++++++++++--
Acked-by: Wei Liu <wei.l...@citrix.com> _______________________________________________ Xen-devel mailing list Xen-devel@lists.xenproject.org https://lists.xenproject.org/mailman/listinfo/xen-devel
