+GLOBAL(hyp_traps_vector_bp_inv)
+ /*
+ * We encode the exception entry in the bottom 3 bits of
+ * SP, and we have to guarantee to be 8 bytes aligned.
+ */
+ add sp, sp, #1 /* Reset 7 */
+ add sp, sp, #1 /* Undef 6 */
+ add sp, sp, #1 /* Hypervisor Call 5 */
+ add sp, sp, #1 /* Prefetch abort 4 */
+ add sp, sp, #1 /* Data abort 3 */
+ add sp, sp, #1 /* Hypervisor 2 */
+ add sp, sp, #1 /* IRQ 1 */
+ nop /* FIQ 0 */
+
+ mcr p15, 0, r0, c7, c5, 6 /* BPIALL */
+ isb
+
+ /*
+ * As we cannot use any temporary registers and cannot
+ * clobber SP, we can decode the exception entry using
+ * an unrolled binary search.
+ */
+ tst sp, #4
+ bne 1f
+
+ tst sp, #2
+ bne 3f
+
+ tst sp, #1
+ bic sp, sp, #0x7
+ bne trap_irq
+ b trap_fiq
+
+1:
+ tst sp, #2
+ bne 2f
+
+ tst sp, #1
+ bic sp, sp, #0x7
+ bne trap_hypervisor_call
+ b trap_prefetch_abort
+
+2:
+ tst sp, #1
+ bic sp, sp, #0x7
+ bne trap_reset
+ b trap_undefined_instruction
+
+3:
+ tst sp, #1
+ bic sp, sp, #0x7
+ bne trap_data_abort
+ b trap_guest_sync