>>> On 19.02.18 at 18:51, <[email protected]> wrote: > We're noticing a reproducible system boot hang on certain > Skylake platforms where the BIOS is configured in legacy > boot mode with x2APIC disabled. The system stalls immediately > after writing the first SMP initialization sequence into APIC ICR. > > The cause of the problem is watchdog NMI handler execution - > somewhere near the end of NMI handling (after it's already > rescheduled the next NMI) it tries to access IO port 0x61 > to get the actual NMI reason on CPU0. Unfortunately, this > port is emulated by BIOS using SMIs and this emulation for > some reason takes more time than we expect during INIT-SIPI-SIPI > sequence. As the result, the system is constantly moving between > NMI and SMI handler and not making any progress. > > To avoid this, initialize the watchdog after SMP bootstrap on > CPU0 and, additionally, protect the NMI handler by moving > IO port access before NMI re-scheduling. The latter should also > help in case of post boot CPU onlining. Although we're running > watchdog at much lower frequency at this point, it's neveretheless > possible we may trigger the issue anyway. > > Signed-off-by: Igor Druzhinin <[email protected]>
Reviewed-by: Jan Beulich <[email protected]> _______________________________________________ Xen-devel mailing list [email protected] https://lists.xenproject.org/mailman/listinfo/xen-devel
