While I (quite obviously) don't have any suitable hardware, Intel's
SDE allows testing the implementation. And since there's no new
state (registers) associated with this ISA extension, this should
suffice for integration.
01: CPUID: AVX512-FP16 definitions
02: handle AVX512-FP16 insns encoded in 0f3a opcode map
03: handle AVX512-FP16 Map5 arithmetic insns
04: handle AVX512-FP16 move insns
05: handle AVX512-FP16 fma-like insns
06: handle AVX512-FP16 Map6 misc insns
07: handle AVX512-FP16 complex multiplication insns
08: handle AVX512-FP16 conversion to/from (packed) int16 insns
09: handle AVX512-FP16 floating point conversion insns
10: handle AVX512-FP16 conversion to/from (packed) int{32,64} insns
11: AVX512-FP16 testing
While I've re-based this ahead of the also pending AMX series (and,
obviously, ahead of the not even submitted yet KeyLocker one), this
series is intentionally built on top of "x86emul: a few small steps
towards disintegration", which has already been pending for far too
long.
Jan
