> From: Andrew Cooper <andrew.coop...@citrix.com> > Sent: Monday, January 9, 2023 8:08 PM > > Ice Lake (server at least) has both Arch LBR and model-specific LBR. Sapphire > Rapids does not have model-specific LBR at all. I.e. On SPR and later, > model_specific_lbr will always be NULL, so we must make changes to avoid > reliably hitting the domain_crash(). > > The Arch LBR spec states that CPUs without model-specific LBR implement > MSR_DBG_CTL.LBR by discarding writes and always returning 0. > > Do this for any CPU for which we lack model-specific LBR information. > > Adjust the now-stale comment, now that the Arch LBR spec has created a > way to > signal "no model specific LBR" to guests. > > Signed-off-by: Andrew Cooper <andrew.coop...@citrix.com>
Reviewed-by: Kevin Tian <kevin.t...@intel.com>
