Hi Luca, > On 23 May 2023, at 09:43, Luca Fancellu <luca.fance...@arm.com> wrote: > > Arm now can use the "dom0=" Xen command line option and the support > for guests running SVE instructions is added, put entries in the > changelog. > > Mention the "Tech Preview" status and add an entry in SUPPORT.md > > Signed-off-by: Luca Fancellu <luca.fance...@arm.com> > Acked-by: Henry Wang <henry.w...@arm.com> # CHANGELOG
Reviewed-by: Bertrand Marquis <bertrand.marq...@arm.com> Cheers Bertrand > --- > Changes from v6: > - Add Henry's A-by to CHANGELOG > Changes from v5: > - Add Tech Preview status and add entry in SUPPORT.md (Bertrand) > Changes from v4: > - No changes > Change from v3: > - new patch > --- > CHANGELOG.md | 3 +++ > SUPPORT.md | 6 ++++++ > 2 files changed, 9 insertions(+) > > diff --git a/CHANGELOG.md b/CHANGELOG.md > index 5bfd3aa5c0d5..512b7bdc0fcb 100644 > --- a/CHANGELOG.md > +++ b/CHANGELOG.md > @@ -11,6 +11,8 @@ The format is based on [Keep a > Changelog](https://keepachangelog.com/en/1.0.0/) > cap toolstack provided values. > - Ignore VCPUOP_set_singleshot_timer's VCPU_SSHOTTMR_future flag. The only > known user doesn't use it properly, leading to in-guest breakage. > + - The "dom0" option is now supported on Arm and "sve=" sub-option can be > used > + to enable dom0 guest to use SVE/SVE2 instructions. > > ### Added > - On x86, support for features new in Intel Sapphire Rapids CPUs: > @@ -20,6 +22,7 @@ The format is based on [Keep a > Changelog](https://keepachangelog.com/en/1.0.0/) > - Bus-lock detection, used by Xen to mitigate (by rate-limiting) the system > wide impact of a guest misusing atomic instructions. > - xl/libxl can customize SMBIOS strings for HVM guests. > + - On Arm, Xen supports guests running SVE/SVE2 instructions. (Tech Preview) > > ## > [4.17.0](https://xenbits.xen.org/gitweb/?p=xen.git;a=shortlog;h=RELEASE-4.17.0) > - 2022-12-12 > > diff --git a/SUPPORT.md b/SUPPORT.md > index 6dbed9d5d029..e0fa2246807b 100644 > --- a/SUPPORT.md > +++ b/SUPPORT.md > @@ -99,6 +99,12 @@ Extension to the GICv3 interrupt controller to support MSI. > > Status: Experimental > > +### ARM Scalable Vector Extension (SVE/SVE2) > + > +AArch64 guest can use Scalable Vector Extension (SVE/SVE2). > + > + Status: Tech Preview > + > ## Guest Type > > ### x86/PV > -- > 2.34.1 >
