On 01/07/2023 10:53, Bernhard Beschow wrote:
Am 30. Juni 2023 08:48:02 UTC schrieb Paolo Bonzini <pbonz...@redhat.com>:
Il mer 28 giu 2023, 13:28 Bernhard Beschow <shen...@gmail.com> ha scritto:
Am 27. Juni 2023 12:07:40 UTC schrieb Olaf Hering <o...@aepfle.de>:
Tue, 27 Jun 2023 10:12:50 +0000 Bernhard Beschow <shen...@gmail.com>:
The BAR is a 32 bit register whose default value is 0x00000001. I think
what's supposed to happen here is a pci_set_long() rather than a
pci_set_byte().
Indeed, the u32 at that address changes from c121 to c101 with the
current code.
Neat! Would you mind sending a patch fixing the BMIBA register to be reset
as 32 bit?
I think we should also check why writing the command register is not
disabling the BAR as well.
So IIUC the BMIBA register is managed internally by QEMU's PCI code and we
shouldn't have to mess with the register at all. We should actually remove the
explicit reset of BMIBA, correct?
I've tried debugging the PCI code when working on the VIA IDE controller to
understand it better. But despite QEMU being compiled with --enable-debug it
seemd to be compiled with -O2 still, making debugging quite hard. I'm not sure
if any compile flags leak into my build environment though.
Certainly --enable-debug normally does the right thing when building QEMU. If you
want to double-check the compiler flags in use to see if anything from CFLAGS/LDFLAGS
is getting picked up, use "make V=1" after configure which outputs the full command
being used during the build rather than just the summary.
ATB,
Mark.
