Interrupt status introduced in PCI 2.3 Immediate readiness introduced in PCIe 4.0
Signed-off-by: Stewart Hildebrand <stewart.hildebr...@amd.com> --- v4->v5: * new patch --- xen/include/xen/pci_regs.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/xen/include/xen/pci_regs.h b/xen/include/xen/pci_regs.h index a90aff1712ba..84b18736a85d 100644 --- a/xen/include/xen/pci_regs.h +++ b/xen/include/xen/pci_regs.h @@ -50,6 +50,8 @@ #define PCI_COMMAND_INTX_DISABLE 0x400 /* INTx Emulation Disable */ #define PCI_STATUS 0x06 /* 16 bits */ +#define PCI_STATUS_IMM_READY 0x01 /* Immediate Readiness */ +#define PCI_STATUS_INTERRUPT 0x08 /* Interrupt status */ #define PCI_STATUS_CAP_LIST 0x10 /* Support Capability List */ #define PCI_STATUS_66MHZ 0x20 /* Support 66 Mhz PCI 2.1 bus */ #define PCI_STATUS_UDF 0x40 /* Support User Definable Features [obsolete] */ -- 2.42.0
