On 13.09.2023 16:35, Stewart Hildebrand wrote: > Introduce a handler for the PCI status register, with ability to mask the > capabilities bit. The status register contains RsvdZ bits, read-only bits, and > write-1-to-clear bits, so introduce bitmasks to handle these in vPCI. If a bit > in the bitmask is set, then the special meaning applies: > > rsvdz_mask: read as zero, guest write ignore (write zero to hardware) > ro_mask: read normal, guest write ignore (preserve on write to hardware) > rw1c_mask: read normal, write 1 to clear > > The RsvdZ naming was borrowed from the PCI Express Base 4.0 specification. > > Xen preserves the value of read-only bits on write to hardware, discarding the > guests write value. > > The mask_cap_list flag will be set in a follow-on patch. > > Signed-off-by: Stewart Hildebrand <stewart.hildebr...@amd.com>
Reviewed-by: Jan Beulich <jbeul...@suse.com>
