On 15.12.2023 15:18, Roger Pau Monne wrote:
> However take into account the minimum number of levels required by unity maps
> when setting the page table levels.
>
> The previous setting of the page table levels for PV guests based on the
> highest RAM address was bogus, as there can be other non-RAM regions past the
> highest RAM address that need to be mapped, for example device MMIO.
>
> For HVM we also take amd_iommu_min_paging_mode into account, however if unity
> maps require more than 4 levels attempting to add those will currently fail at
> the p2m level, as 4 levels is the maximum supported.
>
> Fixes: 0700c962ac2d ('Add AMD IOMMU support into hypervisor')
> Signed-off-by: Roger Pau Monné <roger....@citrix.com>
Reviewed-by: Jan Beulich <jbeul...@suse.com>
with one remark:
> --- a/xen/drivers/passthrough/amd/pci_amd_iommu.c
> +++ b/xen/drivers/passthrough/amd/pci_amd_iommu.c
> @@ -359,21 +359,17 @@ int __read_mostly amd_iommu_min_paging_mode = 1;
> static int cf_check amd_iommu_domain_init(struct domain *d)
> {
> struct domain_iommu *hd = dom_iommu(d);
> + int pglvl = amd_iommu_get_paging_mode(
> + PFN_DOWN(1UL << domain_max_paddr_bits(d)));
This would feel safer as
1UL << (domain_max_paddr_bits(d) - PAGE_SHIFT)
as then not being prone to UB should the function ever become capable
of returning 64.
Jan
