Support for specifying "raw" insns was added only in 2.38.
To support older version it would be better switch to .insn
with operands.
The following compilation error occurs:
./arch/riscv/include/asm/processor.h: Assembler messages:
./arch/riscv/include/asm/processor.h:70: Error: unrecognized opcode
`0x0100000F'
In case of the following Binutils:
$ riscv64-linux-gnu-as --version
GNU assembler (GNU Binutils for Debian) 2.35.2
Suggested-by: Andrew Cooper <andrew.coop...@citrix.com>
Signed-off-by: Oleksii Kurochko <oleksii.kuroc...@gmail.com>
Suggested-by: Jan Beulich <jbeul...@suse.com>
---
Andrew,
Could you please take a look if you are okay with suggested
changes.
Thanks in advance.
---
Changes in V14:
- add Suggested-By: Jan Beulich <jbeul...@suse.com>
- switch from "raw" insn to .insn with operands to support older gas.
---
Changes in V13:
- new patch
---
xen/arch/riscv/include/asm/processor.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/xen/arch/riscv/include/asm/processor.h
b/xen/arch/riscv/include/asm/processor.h
index 6846151717..3ae164c265 100644
--- a/xen/arch/riscv/include/asm/processor.h
+++ b/xen/arch/riscv/include/asm/processor.h
@@ -67,7 +67,7 @@ static inline void cpu_relax(void)
__asm__ __volatile__ ( "pause" );
#else
/* Encoding of the pause instruction */
- __asm__ __volatile__ ( ".insn 0x0100000F" );
+ __asm__ __volatile__ ( ".insn r MISC_MEM, 0, 0, x0, x0, x16" );
#endif
barrier();
--
2.45.2
