On 27/11/2024 8:38 am, Roger Pau Monné wrote: > On Tue, Nov 26, 2024 at 08:58:59PM +0000, Andrew Cooper wrote: >> The SDM instructs software to write 0 to ESR prior to reading it. However, >> due to an original Pentium erratum, most logic skips the write based on there >> being more than 3 LVTs; a stand-in to identify the Pentium. >> >> Xen, being 64bit, doesn't need compatibility for i586 processors. >> >> Introduce a new apic_read_esr() helper, quoting the SDM to explain why a >> function named apic_read_esr() has a write in it too. >> >> Use the new helper throughout apic.c and smpboot.c, which allows us to remove >> some useless reads of APIC_LVR. This in turn removes the external callers of >> get_maxlvt(), so make it local to apic.c >> >> No practical change. >> >> Signed-off-by: Andrew Cooper <[email protected]> > Acked-by: Roger Pau Monné <[email protected]> > > Just a couple of nits.
Thanks, but I'm going to intentionally defer the ancillary cleanup for later. Yes it should be done, but; while I'm very confident about the fix, if it does turn out to break something then I don't want to be "was it a different errata, or was it an integer handling change" because both will be nasty. ~Andrew
