On 30.05.2025 15:17, Sergii Dmytruk wrote: > --- a/xen/arch/x86/boot/trampoline.S > +++ b/xen/arch/x86/boot/trampoline.S > @@ -71,6 +71,27 @@ trampoline_protmode_entry: > mov $X86_CR4_PAE,%ecx > mov %ecx,%cr4 > > + /* > + * Get APIC ID while we're in non-paged mode. Start by checking if > + * x2APIC is enabled. > + */ > + mov $MSR_APIC_BASE, %ecx > + rdmsr > + test $APIC_BASE_EXTD, %eax > + jnz .Lx2apic > + > + /* Not x2APIC, read from MMIO */ > + and $APIC_BASE_ADDR_MASK, %eax > + mov APIC_ID(%eax), %esp > + shr $24, %esp
I have to admit that I'm rather hesitant towards seeing %esp used like this. > --- a/xen/arch/x86/boot/x86_64.S > +++ b/xen/arch/x86/boot/x86_64.S > @@ -15,7 +15,33 @@ ENTRY(__high_start) > mov $XEN_MINIMAL_CR4,%rcx > mov %rcx,%cr4 > > - mov stack_start(%rip),%rsp > + test %ebx,%ebx > + cmovz stack_start(%rip), %rsp > + jz .L_stack_set > + > + /* APs only: get stack base from APIC ID saved in %esp. */ > + mov $-1, %rax Here and below 32-bit insn would do fine. However, ... > + lea x86_cpu_to_apicid(%rip), %rcx > +1: > + add $1, %rax > + cmp $NR_CPUS, %eax > + jb 2f > + hlt > +2: > + cmp %esp, (%rcx, %rax, 4) > + jne 1b ... can't all of this be a simple REPNE SCASL? As to the upper bound of NR_CPUS, do we really need to look this far? > + /* %eax is now Xen CPU index. */ > + lea stack_base(%rip), %rcx > + mov (%rcx, %rax, 8), %rsp > + > + test %rsp,%rsp Nit: Blank after comma please. Jan
