On 22/01/2026 4:49 pm, Alejandro Vallejo wrote:
> With cross-vendor support gone, it's no longer needed.
>
> Signed-off-by: Alejandro Vallejo <[email protected]>
You're not really dropping or altering the SYSENTER behaviour. You're
dropping the emulation of Intel's MSR behaviour on AMD systems.
And this comes which a subtle change in behaviour that is relevant to
point out.
Notably, AMD prohibit the use of the SYSENTER and SYSEXIT instructions
outside of Long mode, and they're behaviour for MSR_SEL_* still follows
the 32bit model where the upper half is write-discard. AMD CPUs really
do only have 32 bits of storage for the 3 MSRs, and unlike Intel, did
not extend it to 64 bits of storage to support Long Mode.
Xen previously (and unconditionally, irrespective of same or cross
vendor configuration) emulated Intel behaviour on AMD CPUs.
I think this is even a latent bug; on hardware that supports
vVM{LOAD,SAVE}, the intercept doesn't trigger anyway, and this whole
emulation falls apart anyway.
Something which is very much not obvious in the slightest is that the
MSR Intercept bitmaps for VMs apply to the RDMSR/WRMSR instructions
only, and not to implicit MSR accesses such as
SWAPGS/LKGS/WR{FS,GS}BASE, etc.
Anyway,
I think it is necessary to note that VMs which were happening to store
state in the high parts of the SEP MSRs will now lose this state. It is
an ABI change, but it's acceptable because there are almost certainly no
VMs doing this, because it's not how real AMD CPUs behave.
~Andrew
