The trap handlers in hypervisor need to forward events to PV guests if
necessary. If there is no PV guest relevant code should be excluded.
Put code under CONFIG_PV and add ASSERT_UNREACHABLE.
Signed-off-by: Wei Liu <wei.l...@citrix.com>
---
xen/arch/x86/traps.c | 38 ++++++++++++++++++++++++++++++++++++++
1 file changed, 38 insertions(+)
diff --git a/xen/arch/x86/traps.c b/xen/arch/x86/traps.c
index 3988753..6c2729c 100644
--- a/xen/arch/x86/traps.c
+++ b/xen/arch/x86/traps.c
@@ -743,9 +743,13 @@ static void do_trap(struct cpu_user_regs *regs)
if ( guest_mode(regs) )
{
+#ifdef CONFIG_PV
pv_inject_hw_exception(trapnr,
(TRAP_HAVE_EC & (1u << trapnr))
? regs->error_code : X86_EVENT_NO_EC);
+#else
+ ASSERT_UNREACHABLE();
+#endif
return;
}
@@ -974,8 +978,12 @@ void do_invalid_op(struct cpu_user_regs *regs)
if ( likely(guest_mode(regs)) )
{
+#ifdef CONFIG_PV
if ( pv_emulate_invalid_op(regs) )
pv_inject_hw_exception(TRAP_invalid_op, X86_EVENT_NO_EC);
+#else
+ ASSERT_UNREACHABLE();
+#endif
return;
}
@@ -1103,7 +1111,11 @@ void do_int3(struct cpu_user_regs *regs)
return;
}
+#ifdef CONFIG_PV
pv_inject_hw_exception(TRAP_int3, X86_EVENT_NO_EC);
+#else
+ ASSERT_UNREACHABLE();
+#endif
}
static void reserved_bit_page_fault(unsigned long addr,
@@ -1140,6 +1152,7 @@ static int handle_ldt_mapping_fault(unsigned int offset,
if ( !guest_mode(regs) )
return 0;
+#ifdef CONFIG_PV
/* Access would have become non-canonical? Pass #GP[sel] back. */
if ( unlikely(!is_canonical_address(curr->arch.pv.ldt_base + offset)) )
{
@@ -1151,6 +1164,9 @@ static int handle_ldt_mapping_fault(unsigned int offset,
/* else pass the #PF back, with adjusted %cr2. */
pv_inject_page_fault(regs->error_code,
curr->arch.pv.ldt_base + offset);
+#else
+ ASSERT_UNREACHABLE();
+#endif
}
return EXCRET_fault_fixed;
@@ -1457,7 +1473,11 @@ void do_page_fault(struct cpu_user_regs *regs)
if ( unlikely(regs->error_code & PFEC_reserved_bit) )
reserved_bit_page_fault(addr, regs);
+#ifdef CONFIG_PV
pv_inject_page_fault(regs->error_code, addr);
+#else
+ ASSERT_UNREACHABLE();
+#endif
}
/*
@@ -1494,7 +1514,9 @@ void __init do_early_page_fault(struct cpu_user_regs
*regs)
void do_general_protection(struct cpu_user_regs *regs)
{
+#ifdef CONFIG_PV
struct vcpu *v = current;
+#endif
unsigned long fixup;
if ( debugger_trap_entry(TRAP_gp_fault, regs) )
@@ -1506,6 +1528,7 @@ void do_general_protection(struct cpu_user_regs *regs)
if ( !guest_mode(regs) )
goto gp_in_kernel;
+#ifdef CONFIG_PV
/*
* Cunning trick to allow arbitrary "INT n" handling.
*
@@ -1556,6 +1579,9 @@ void do_general_protection(struct cpu_user_regs *regs)
/* Pass on GPF as is. */
pv_inject_hw_exception(TRAP_gp_fault, regs->error_code);
+#else
+ ASSERT_UNREACHABLE();
+#endif
return;
gp_in_kernel:
@@ -1744,7 +1770,9 @@ void unset_nmi_callback(void)
void do_device_not_available(struct cpu_user_regs *regs)
{
+#ifdef CONFIG_PV
struct vcpu *curr = current;
+#endif
if ( !guest_mode(regs) )
{
@@ -1762,6 +1790,7 @@ void do_device_not_available(struct cpu_user_regs *regs)
return;
}
+#ifdef CONFIG_PV
vcpu_restore_fpu_lazy(curr);
if ( curr->arch.pv.ctrlreg[0] & X86_CR0_TS )
@@ -1771,6 +1800,9 @@ void do_device_not_available(struct cpu_user_regs *regs)
}
else
TRACE_0D(TRC_PV_MATH_STATE_RESTORE);
+#else
+ ASSERT_UNREACHABLE();
+#endif
return;
}
@@ -1778,7 +1810,9 @@ void do_device_not_available(struct cpu_user_regs *regs)
void do_debug(struct cpu_user_regs *regs)
{
unsigned long dr6;
+#ifdef CONFIG_PV
struct vcpu *v = current;
+#endif
/* Stash dr6 as early as possible. */
dr6 = read_debugreg(6);
@@ -1888,11 +1922,15 @@ void do_debug(struct cpu_user_regs *regs)
return;
}
+#ifdef CONFIG_PV
/* Save debug status register where guest OS can peek at it */
v->arch.debugreg[6] |= (dr6 & ~X86_DR6_DEFAULT);
v->arch.debugreg[6] &= (dr6 | ~X86_DR6_DEFAULT);
pv_inject_hw_exception(TRAP_debug, X86_EVENT_NO_EC);
+#else
+ ASSERT_UNREACHABLE();
+#endif
}
static void __init noinline __set_intr_gate(unsigned int n,
--
git-series 0.9.1
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