> -----Original Message----- > From: Stefano Stabellini [mailto:sstabell...@kernel.org] > Sent: 2019年2月6日 5:39 > To: xen-devel@lists.xenproject.org > Cc: sstabell...@kernel.org; Stefano Stabellini <stefa...@xilinx.com>; > julien.gr...@arm.com; Peng Fan <peng....@nxp.com>; jgr...@suse.com > Subject: [PATCH for-4.12] xen/arm: gic-v2: deactivate interrupts during > initialization > > Interrupts could be ACTIVE at boot. Make sure to deactivate them during > initialization. > > Signed-off-by: Stefano Stabellini <stefa...@xilinx.com> > CC: julien.gr...@arm.com > CC: peng....@nxp.com > CC: jgr...@suse.com > --- > xen/arch/arm/gic-v2.c | 4 ++++ > 1 file changed, 4 insertions(+) > > diff --git a/xen/arch/arm/gic-v2.c b/xen/arch/arm/gic-v2.c index > e9fb8a0..256988c 100644 > --- a/xen/arch/arm/gic-v2.c > +++ b/xen/arch/arm/gic-v2.c > @@ -379,7 +379,10 @@ static void __init gicv2_dist_init(void) > > /* Disable all global interrupts */ > for ( i = 32; i < nr_lines; i += 32 ) > + { > writel_gicd(~0x0, GICD_ICENABLER + (i / 32) * 4); > + writel_gicd(~0x0, GICD_ICACTIVER + (i / 32) * 4); > + } > > /* Turn on the distributor */ > writel_gicd(GICD_CTL_ENABLE, GICD_CTLR); @@ -394,6 +397,7 @@ > static void gicv2_cpu_init(void) > /* The first 32 interrupts (PPI and SGI) are banked per-cpu, so > * even though they are controlled with GICD registers, they must > * be set up here with the other per-cpu state. */ > + writel_gicd(0xffffffff, GICD_ICACTIVER); /* Diactivate PPIs and > + SGIs */ > writel_gicd(0xffff0000, GICD_ICENABLER); /* Disable all PPI */ > writel_gicd(0x0000ffff, GICD_ISENABLER); /* Enable all SGI */ > > --
Reviewed-by: Peng Fan <peng....@nxp.com> > 1.9.1 _______________________________________________ Xen-devel mailing list Xen-devel@lists.xenproject.org https://lists.xenproject.org/mailman/listinfo/xen-devel
