The Hygon Dhyana CPU has the same speculative execution as AMD family 17h, so share AMD Retpoline and PTI mitigation code with Hygon Dhyana.
Signed-off-by: Pu Wen <pu...@hygon.cn> Acked-by: Jan Beulich <jbeul...@suse.com> --- xen/arch/x86/spec_ctrl.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/xen/arch/x86/spec_ctrl.c b/xen/arch/x86/spec_ctrl.c index 1171c02..1cd7903 100644 --- a/xen/arch/x86/spec_ctrl.c +++ b/xen/arch/x86/spec_ctrl.c @@ -306,7 +306,8 @@ static bool __init retpoline_safe(uint64_t caps) { unsigned int ucode_rev = this_cpu(ucode_cpu_info).cpu_sig.rev; - if ( boot_cpu_data.x86_vendor == X86_VENDOR_AMD ) + if ( boot_cpu_data.x86_vendor == X86_VENDOR_AMD || + boot_cpu_data.x86_vendor == X86_VENDOR_HYGON ) return true; if ( boot_cpu_data.x86_vendor != X86_VENDOR_INTEL || @@ -632,7 +633,8 @@ int8_t __read_mostly opt_xpti_domu = -1; static __init void xpti_init_default(uint64_t caps) { - if ( boot_cpu_data.x86_vendor == X86_VENDOR_AMD ) + if ( boot_cpu_data.x86_vendor == X86_VENDOR_AMD || + boot_cpu_data.x86_vendor == X86_VENDOR_HYGON ) caps = ARCH_CAPS_RDCL_NO; if ( caps & ARCH_CAPS_RDCL_NO ) -- 2.7.4 _______________________________________________ Xen-devel mailing list Xen-devel@lists.xenproject.org https://lists.xenproject.org/mailman/listinfo/xen-devel